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[PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions
From: |
Frédéric Pétrot |
Subject: |
[PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions |
Date: |
Mon, 25 Oct 2021 14:28:10 +0200 |
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 070db77ca5..b183ad2b6e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -426,7 +426,15 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
func(dest, src1, a->imm);
- gen_set_gpr(ctx, a->rd, dest);
+ if (get_xl(ctx) == MXL_RV128) {
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv desth = dest_gprh(ctx, a->rd);
+
+ func(desth, src1h, -(a->imm < 0));
+ gen_set_gpr128(ctx, a->rd, dest, desth);
+ } else {
+ gen_set_gpr(ctx, a->rd, dest);
+ }
return true;
}
@@ -440,7 +448,16 @@ static bool gen_logic(DisasContext *ctx, arg_r *a,
DisasExtend ext,
func(dest, src1, src2);
- gen_set_gpr(ctx, a->rd, dest);
+ if (get_xl(ctx) == MXL_RV128) {
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv src2h = get_gprh(ctx, a->rs2);
+ TCGv desth = dest_gprh(ctx, a->rd);
+
+ func(desth, src1h, src2h);
+ gen_set_gpr128(ctx, a->rd, dest, desth);
+ } else {
+ gen_set_gpr(ctx, a->rd, dest);
+ }
return true;
}
--
2.33.0
- [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, (continued)
- [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, Frédéric Pétrot, 2021/10/25
- [PATCH v4 03/17] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/25
- [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/25
- [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/25
- [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions,
Frédéric Pétrot <=
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
- [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/25
- [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/25