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From: | Richard Henderson |
Subject: | Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers |
Date: | Wed, 20 Oct 2021 07:44:33 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 |
On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> --- target/riscv/cpu.h | 1 + target/riscv/translate.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c24bc9a039..c8b98f1b70 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -109,6 +109,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)struct CPURISCVState {target_ulong gpr[32]; + target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
At first I was going to suggest that the 128-bit value be represented in host byte order, but then I thought that would just get in the way until such any such host operations are apparent.
You are missing an update to machine.c for migration (and probably more importantly, loadvm/savevm for debugging). I think you'll want to put these into a separate subsection, controlled by misa_mxl_max == RV128.
for (i = 1; i < 32; i++) { cpu_gpr[i] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); + cpu_gprh[i] = tcg_global_mem_new(cpu_env, + offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
This will just be confusing in the tcg dumps -- let's not name the two temps the identically.Honestly, I'm not 100% thrilled about the / that appears in the current name; I think it would be easiest to do
g_string_printf("x%d", i) and g_string_printf("x%dh", i) r~
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