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[PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit re
From: |
Frédéric Pétrot |
Subject: |
[PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers |
Date: |
Tue, 19 Oct 2021 11:47:57 +0200 |
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 1 +
target/riscv/translate.c | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c24bc9a039..c8b98f1b70 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -109,6 +109,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
+ target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
uint64_t fpr[32]; /* assume both F and D extensions */
/* vector coprocessor state. */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3c2e9fb790..b64fe8470d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -32,7 +32,7 @@
#include "instmap.h"
/* global register indices */
-static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -755,10 +755,13 @@ void riscv_translate_init(void)
* unless you specifically block reads/writes to reg 0.
*/
cpu_gpr[0] = NULL;
+ cpu_gprh[0] = NULL;
for (i = 1; i < 32; i++) {
cpu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
+ cpu_gprh[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
}
for (i = 0; i < 32; i++) {
--
2.33.0
- [PATCH v3 00/21] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/19
- [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values, Frédéric Pétrot, 2021/10/19
- [PATCH v3 04/21] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/19
- [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/19
- [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers,
Frédéric Pétrot <=
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/19
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19