Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for

From:	Richard Henderson
Subject:	Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
Date:	Sun, 17 Oct 2021 22:38:01 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/17/21 3:55 PM, Alistair Francis wrote:

On Fri, Oct 15, 2021 at 5:50 PM <frank.chang@sifive.com> wrote:


From: Frank Chang <frank.chang@sifive.com>

TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.

Signed-off-by: Frank Chang <frank.chang@sifive.com>


Reviewed-by: Alistair Francis <alistair.francis@wdc.com>


BTW, Alistair, I think this bug fix should be cherry-picked out of this patch 
set right away.


r~

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v8 00/78] support vector extension v1.0, frank . chang, 2021/10/15
- [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, frank . chang, 2021/10/15
  - Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, Richard Henderson, 2021/10/15
  - Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, Alistair Francis, 2021/10/17
    - Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, Richard Henderson <=
  - Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, Alistair Francis, 2021/10/18
- [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/10/15
- [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/10/15
- [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/10/15
- [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/10/15
- [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/10/15
- [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/10/15
- [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/10/15

Prev by Date: Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
Next by Date: Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
Previous by thread: Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
Next by thread: Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
Index(es):
- Date
- Thread