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[PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support
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From: |
frank . chang |
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Subject: |
[PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support |
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Date: |
Fri, 15 Oct 2021 15:45:03 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 10 +++++-----
target/riscv/cpu.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 89a612f7606..36448e61572 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -492,7 +492,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
target_misa |= RVH;
}
if (cpu->cfg.ext_v) {
- int vext_version = VEXT_VERSION_0_07_1;
+ int vext_version = VEXT_VERSION_1_00_0;
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
@@ -517,8 +517,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
- vext_version = VEXT_VERSION_0_07_1;
+ if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
+ vext_version = VEXT_VERSION_1_00_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
@@ -527,7 +527,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
} else {
qemu_log("vector version is not specified, "
- "use the default value v0.7.1\n");
+ "use the default value v1.0\n");
}
set_vext_version(env, vext_version);
}
@@ -591,6 +591,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+ DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
/* This is experimental so mark with 'x-' */
@@ -599,7 +600,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
- DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d63a08b6e4c..8ded9da5623 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -82,7 +82,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define VEXT_VERSION_0_07_1 0x00000701
+#define VEXT_VERSION_1_00_0 0x00010000
enum {
TRANSLATE_SUCCESS,
--
2.25.1
- [PATCH v8 00/78] support vector extension v1.0, frank . chang, 2021/10/15
- [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, frank . chang, 2021/10/15
- [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support,
frank . chang <=
- [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/10/15
- [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/10/15
- [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/10/15
- [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/10/15
- [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/10/15
- [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/10/15
- [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/10/15
- [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/10/15