Re: [PATCH 00/17] target/riscv: Use tcg_constant_*

[LIU Zhiwei]

On 2021/7/9 下午12:25, Richard Henderson wrote:
> Replace use of tcg_const_*, which makes a copy into a temp
> which must be freed, with direct use of the constant.
>
> Reorg handling of $zero, with different accessors for
> source and destination.
>
> Reorg handling of csrs, passing the actual write_mask
> instead of a regno.
>
> Use more helpers for RVH expansion.

Hi Richard,

In patch 09-17  target/riscv: Reorg csr instruction,  I think the 
parameter name 'rc'  can be renamed to 'csrno'.

Otherwise,
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Also on a side note, could you give me some advice for the following 
question?

I have been supporting  running 32bit application on qemu-riscv64. After 
this patch set,
it is hard to define a  method,  such as gpr_dst_s or gpr_dst_u, to 
extend the destination
register. I can only extend the destination register(ext32s or ext32u) 
in each instruction
with scattered code.

Can we just omit the extension of the destination register?

Best Regards,
Zhiwei



> r~
>
>
> Richard Henderson (17):
>    target/riscv: Use tcg_constant_*
>    target/riscv: Introduce gpr_src, gpr_dst
>    target/riscv: Use gpr_{src,dst} in shift operations
>    target/riscv: Use gpr_{src,dst} in word division operations
>    target/riscv: Use gpr_{src,dst} and tcg_constant_tl in gen_grevi
>    target/riscv: Use gpr_src in branches
>    target/riscv: Use gpr_{src,dst} for integer load/store
>    target/riscv: Use gpr_{src,dst} for word shift operations
>    target/riscv: Reorg csr instructions
>    target/riscv: Use gpr_{src,dst} for RVA
>    target/riscv: Use gpr_{src,dst} for RVB
>    target/riscv: Use gpr_{src,dst} for RVF
>    target/riscv: Use gpr_{src,dst} for RVD
>    target/riscv: Tidy trans_rvh.c.inc
>    target/riscv: Use gen_arith for mulh and mulhu
>    target/riscv: Use gpr_{src,dst} for RVV
>    target/riscv: Remove gen_get_gpr
>
>   target/riscv/helper.h                   |   6 +-
>   target/riscv/insn32.decode              |   1 +
>   target/riscv/op_helper.c                |  18 +-
>   target/riscv/translate.c                | 273 +++++++++-----------
>   target/riscv/insn_trans/trans_rva.c.inc |  42 ++--
>   target/riscv/insn_trans/trans_rvb.c.inc |  11 +-
>   target/riscv/insn_trans/trans_rvd.c.inc | 116 ++++-----
>   target/riscv/insn_trans/trans_rvf.c.inc | 134 ++++------
>   target/riscv/insn_trans/trans_rvh.c.inc | 264 ++++---------------
>   target/riscv/insn_trans/trans_rvi.c.inc | 322 ++++++++++++++----------
>   target/riscv/insn_trans/trans_rvm.c.inc |  24 +-
>   target/riscv/insn_trans/trans_rvv.c.inc | 144 ++++-------
>   12 files changed, 534 insertions(+), 821 deletions(-)