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Re: [RFC 09/15] target/riscv: rvb: shift ones
From: |
Richard Henderson |
Subject: |
Re: [RFC 09/15] target/riscv: rvb: shift ones |
Date: |
Thu, 19 Nov 2020 12:54:59 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool trans_slo(DisasContext *ctx, arg_slo *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, &gen_slo);
> +}
> +
> +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + return gen_arith_shamt_tl(ctx, a, &gen_slo);
> +}
> +
> +static bool trans_sro(DisasContext *ctx, arg_sro *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, &gen_sro);
> +}
> +
> +static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + return gen_arith_shamt_tl(ctx, a, &gen_sro);
> +}
Use the same gen_shift family of functions discussed vs patch 8.
r~
- Re: [RFC 05/15] target/riscv: rvb: pack two words into one register, (continued)
- [RFC 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/11/18
- [RFC 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/11/18
- [RFC 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/11/18
- [RFC 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/11/18
- Re: [RFC 09/15] target/riscv: rvb: shift ones,
Richard Henderson <=
- [RFC 10/15] target/riscv: rvb: rotate (left/right), frank . chang, 2020/11/18
- [RFC 11/15] target/riscv: rvb: generalized reverse, frank . chang, 2020/11/18
- [RFC 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/11/18
- [RFC 13/15] target/riscv: rvb: address calculation, frank . chang, 2020/11/18
- [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend, frank . chang, 2020/11/18