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[PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv inst
From: |
Alistair Francis |
Subject: |
[PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions |
Date: |
Sun, 26 Apr 2020 09:19:31 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 54 +++++++++++++++------------------------
1 file changed, 21 insertions(+), 33 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 075675c59c..2ac599505f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env,
hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
+ if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
+ use_background = true;
+ }
+
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
-
- if (riscv_has_ext(env, RVH) &&
- MSTATUS_MPV_ISSET(env)) {
- use_background = true;
- }
- }
- }
-
- if (mode == PRV_S && access_type != MMU_INST_FETCH &&
- riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
- if (get_field(env->hstatus, HSTATUS_SPRV)) {
- mode = get_field(env->mstatus, SSTATUS_SPP);
- use_background = true;
}
}
@@ -727,8 +718,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
hwaddr pa = 0;
int prot, prot2;
bool pmp_violation = false;
- bool m_mode_two_stage = false;
- bool hs_mode_two_stage = false;
bool first_stage_error = true;
int ret = TRANSLATE_FAIL;
int mode = mmu_idx;
@@ -738,30 +727,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- /*
- * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
- * set and we want to access a virtulisation address.
- */
- if (riscv_has_ext(env, RVH)) {
- m_mode_two_stage = env->priv == PRV_M &&
- access_type != MMU_INST_FETCH &&
- get_field(env->mstatus, MSTATUS_MPRV) &&
- MSTATUS_MPV_ISSET(env);
-
- hs_mode_two_stage = env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env) &&
- access_type != MMU_INST_FETCH &&
- get_field(env->hstatus, HSTATUS_SPRV) &&
- get_field(env->hstatus, HSTATUS_SPV);
- }
-
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
}
- if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+ access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ MSTATUS_MPV_ISSET(env)) {
+ riscv_cpu_set_two_stage_lookup(env, true);
+ }
+
+ if (riscv_cpu_virt_enabled(env) ||
+ (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address, access_type,
mmu_idx, true, true);
@@ -813,6 +793,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
__func__, address, ret, pa, prot);
}
+ /* We did the two stage lookup based on MPRV, unset the lookup */
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+ access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ MSTATUS_MPV_ISSET(env)) {
+ riscv_cpu_set_two_stage_lookup(env, false);
+ }
+
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--
2.26.2
- [PATCH v1 00/15] RISC-V: Update the Hypervisor spec to v0.6, Alistair Francis, 2020/04/26
- [PATCH v1 02/15] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/04/26
- [PATCH v1 01/15] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/04/26
- [PATCH v1 03/15] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/04/26
- [PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/04/26
- [PATCH v1 04/15] target/riscv: Implement checks for hfence, Alistair Francis, 2020/04/26
- [PATCH v1 06/15] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions,
Alistair Francis <=
- [PATCH v1 08/15] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/04/26
- [PATCH v1 09/15] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/04/26
- [PATCH v1 10/15] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/04/26
- [PATCH v1 12/15] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/04/26
- [PATCH v1 13/15] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/04/26
- [PATCH v1 11/15] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/04/26
- [PATCH v1 14/15] target/riscv: Only support little endian guests, Alistair Francis, 2020/04/26