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[PATCH v1 14/15] target/riscv: Only support little endian guests
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 14/15] target/riscv: Only support little endian guests |
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Date: |
Sun, 26 Apr 2020 09:19:51 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 438d0a61ee..04f3471f2e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -858,6 +858,8 @@ static int read_hstatus(CPURISCVState *env, int csrno,
target_ulong *val)
/* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2);
#endif
+ /* We only support little endian */
+ *val = set_field(*val, HSTATUS_VSBE, 0);
return 0;
}
@@ -869,6 +871,9 @@ static int write_hstatus(CPURISCVState *env, int csrno,
target_ulong val)
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN
options.");
}
#endif
+ if (get_field(val, HSTATUS_VSBE) != 0) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+ }
return 0;
}
--
2.26.2
- [PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status, (continued)
- [PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/04/26
- [PATCH v1 04/15] target/riscv: Implement checks for hfence, Alistair Francis, 2020/04/26
- [PATCH v1 06/15] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 08/15] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/04/26
- [PATCH v1 09/15] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/04/26
- [PATCH v1 10/15] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/04/26
- [PATCH v1 12/15] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/04/26
- [PATCH v1 13/15] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/04/26
- [PATCH v1 11/15] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/04/26
- [PATCH v1 14/15] target/riscv: Only support little endian guests,
Alistair Francis <=