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[PATCH] target/riscv: Bugfix reserved bits in PTE for RV64


From: guoren
Subject: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
Date: Tue, 24 Sep 2019 13:00:32 +0800

From: Guo Ren <address@hidden>

Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They can not be a part of ppn.

1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
   4.4 Sv39: Page-Based 39-bit Virtual-Memory System
   4.5 Sv48: Page-Based 48-bit Virtual-Memory System

Signed-off-by: Guo Ren <address@hidden>
Reviewed-by: Liu Zhiwei <address@hidden>
---
 target/riscv/cpu_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6..3c5e8f6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -260,6 +260,7 @@ restart:
         target_ulong pte = ldl_phys(cs->as, pte_addr);
 #elif defined(TARGET_RISCV64)
         target_ulong pte = ldq_phys(cs->as, pte_addr);
+        pte = pte << 10 >> 10;
 #endif
         hwaddr ppn = pte >> PTE_PPN_SHIFT;
 
-- 
2.7.4




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