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Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to
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Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree |
Date: |
Wed, 27 Feb 2019 11:03:05 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
0e1587d723 target/riscv: Remaining rvc insn reuse 32 bit translators
03bc36d2a9 target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
0c1098fa38 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
14f6a21758 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dd6471d6df target/riscv: Convert @cs_2 insns to share translation functions
9022d237a1 target/riscv: Remove decode_RV32_64G()
b3bf7e853b target/riscv: Remove gen_system()
8dafe332ee target/riscv: Rename trans_arith to gen_arith
e536c49e42 target/riscv: Remove manual decoding of RV32/64M insn
a78e0a5ae9 target/riscv: Remove shift and slt insn manual decoding
914e794eb6 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c05621056a target/riscv: Move gen_arith_imm() decoding into trans_* functions
259f1fb44c target/riscv: Remove manual decoding from gen_store()
f36994b013 target/riscv: Remove manual decoding from gen_load()
7898ebce3c target/riscv: Remove manual decoding from gen_branch()
ef4f4af849 target/riscv: Remove gen_jalr()
2b5566b964 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
91de7453ce target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2b6dada763 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2b6165d18b target/riscv: Convert RV priv insns to decodetree
7dc8515d50 target/riscv: Convert RV64D insns to decodetree
f8d03d52f4 target/riscv: Convert RV32D insns to decodetree
82662002b1 target/riscv: Convert RV64F insns to decodetree
f61b8a780c target/riscv: Convert RV32F insns to decodetree
db1a6df36a target/riscv: Convert RV64A insns to decodetree
73fad6f884 target/riscv: Convert RV32A insns to decodetree
f10eed5487 target/riscv: Convert RVXM insns to decodetree
d5af3ac930 target/riscv: Convert RVXI csr insns to decodetree
b7b400c906 target/riscv: Convert RVXI fence insns to decodetree
22a796ba2f target/riscv: Convert RVXI arithmetic insns to decodetree
fa09efd852 target/riscv: Convert RV64I load/store insns to decodetree
30155f3443 target/riscv: Convert RV32I load/store insns to decodetree
654ff5f0ec target/riscv: Convert RVXI branch insns to decodetree
fd945bbb5b target/riscv: Activate decodetree and implemnt LUI & AUIPC
=== OUTPUT BEGIN ===
1/34 Checking commit fd945bbb5b4a (target/riscv: Activate decodetree and
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1884:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 1/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/34 Checking commit 654ff5f0ecfc (target/riscv: Convert RVXI branch insns to
decodetree)
3/34 Checking commit 30155f344314 (target/riscv: Convert RV32I load/store insns
to decodetree)
4/34 Checking commit fa09efd852b6 (target/riscv: Convert RV64I load/store insns
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 4/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/34 Checking commit 22a796ba2fb3 (target/riscv: Convert RVXI arithmetic insns
to decodetree)
6/34 Checking commit b7b400c9063a (target/riscv: Convert RVXI fence insns to
decodetree)
7/34 Checking commit d5af3ac93078 (target/riscv: Convert RVXI csr insns to
decodetree)
8/34 Checking commit f10eed548794 (target/riscv: Convert RVXM insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 169 lines checked
Patch 8/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/34 Checking commit 73fad6f88456 (target/riscv: Convert RV32A insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 199 lines checked
Patch 9/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/34 Checking commit db1a6df36a27 (target/riscv: Convert RV64A insns to
decodetree)
11/34 Checking commit f61b8a780c37 (target/riscv: Convert RV32F insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 442 lines checked
Patch 11/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/34 Checking commit 82662002b162 (target/riscv: Convert RV64F insns to
decodetree)
13/34 Checking commit f8d03d52f4c4 (target/riscv: Convert RV32D insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 398 lines checked
Patch 13/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/34 Checking commit 7dc8515d5033 (target/riscv: Convert RV64D insns to
decodetree)
15/34 Checking commit 2b6165d18b87 (target/riscv: Convert RV priv insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 15/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/34 Checking commit 2b6dada76333 (target/riscv: Convert quadrant 0 of RVXC
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#251: FILE: target/riscv/translate.c:1072:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 231 lines checked
Patch 16/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/34 Checking commit 91de7453ce87 (target/riscv: Convert quadrant 1 of RVXC
insns to decodetree)
18/34 Checking commit 2b5566b96498 (target/riscv: Convert quadrant 2 of RVXC
insns to decodetree)
19/34 Checking commit ef4f4af849b6 (target/riscv: Remove gen_jalr())
20/34 Checking commit 7898ebce3cd2 (target/riscv: Remove manual decoding from
gen_branch())
21/34 Checking commit f36994b0132f (target/riscv: Remove manual decoding from
gen_load())
22/34 Checking commit 259f1fb44ca1 (target/riscv: Remove manual decoding from
gen_store())
23/34 Checking commit c05621056ac7 (target/riscv: Move gen_arith_imm() decoding
into trans_* functions)
24/34 Checking commit 914e794eb635 (target/riscv: make ADD/SUB/OR/XOR/AND insn
use arg lists)
25/34 Checking commit a78e0a5ae9fe (target/riscv: Remove shift and slt insn
manual decoding)
26/34 Checking commit e536c49e42d9 (target/riscv: Remove manual decoding of
RV32/64M insn)
27/34 Checking commit 8dafe332ee78 (target/riscv: Rename trans_arith to
gen_arith)
28/34 Checking commit b3bf7e853b17 (target/riscv: Remove gen_system())
29/34 Checking commit 9022d237a128 (target/riscv: Remove decode_RV32_64G())
30/34 Checking commit dd6471d6dfb9 (target/riscv: Convert @cs_2 insns to share
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:548:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 30/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/34 Checking commit 14f6a21758ed (target/riscv: Convert @cl_d, @cl_w, @cs_d,
@cs_w insns)
32/34 Checking commit 0c1098fa3841 (target/riscv: Splice fsw_sd and flw_ld for
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 309 lines checked
Patch 32/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/34 Checking commit 03bc36d2a9a5 (target/riscv: Splice remaining compressed
insn pairs for riscv32 vs riscv64)
34/34 Checking commit 0e1587d7236a (target/riscv: Remaining rvc insn reuse 32
bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
- [Qemu-riscv] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, (continued)
- [Qemu-riscv] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/02/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, Alistair Francis, 2019/02/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree,
no-reply <=
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27