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[Qemu-riscv] [PATCH v4 28/35] target/riscv: Rename trans_arith to gen_ar
From: |
Bastian Koppelmann |
Subject: |
[Qemu-riscv] [PATCH v4 28/35] target/riscv: Rename trans_arith to gen_arith |
Date: |
Fri, 18 Jan 2019 14:14:49 +0100 |
Signed-off-by: Bastian Koppelmann <address@hidden>
---
v3 -> v4:
- trans_sltu/slt added to conversion
target/riscv/insn_trans/trans_rvi.inc.c | 18 +++++++++---------
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++-------
target/riscv/translate.c | 4 ++--
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 7454c23f74..1d31b6e8b5 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -304,12 +304,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -319,17 +319,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return trans_arith(ctx, a, &gen_slt);
+ return gen_arith(ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return trans_arith(ctx, a, &gen_sltu);
+ return gen_arith(ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- return trans_arith(ctx, a, &tcg_gen_xor_tl);
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -344,12 +344,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- return trans_arith(ctx, a, &tcg_gen_or_tl);
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- return trans_arith(ctx, a, &tcg_gen_and_tl);
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -398,12 +398,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- return trans_arith(ctx, a, &gen_addw);
+ return gen_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- return trans_arith(ctx, a, &gen_subw);
+ return gen_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c
b/target/riscv/insn_trans/trans_rvm.inc.c
index 949f59ddb2..5844d6f5be 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,7 +21,7 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
@@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
- return trans_arith(ctx, a, &gen_mulhsu);
+ return gen_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
@@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
static bool trans_div(DisasContext *ctx, arg_div *a)
{
- return trans_arith(ctx, a, &gen_div);
+ return gen_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
- return trans_arith(ctx, a, &gen_divu);
+ return gen_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
- return trans_arith(ctx, a, &gen_rem);
+ return gen_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
- return trans_arith(ctx, a, &gen_remu);
+ return gen_arith(ctx, a, &gen_remu);
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
- return trans_arith(ctx, a, &gen_mulw);
+ return gen_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6a722a0045..d0b0fca12b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -577,8 +577,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
#endif
-static bool trans_arith(DisasContext *ctx, arg_r *a,
- void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
--
2.20.1
- [Qemu-riscv] [PATCH v4 05/35] target/riscv: Convert RV64I load/store insns to decodetree, (continued)
- [Qemu-riscv] [PATCH v4 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 15/35] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 23/35] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 28/35] target/riscv: Rename trans_arith to gen_arith,
Bastian Koppelmann <=
- [Qemu-riscv] [PATCH v4 22/35] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 20/35] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 10/35] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 31/35] target/riscv: Convert @cs_2 insns to share translation functions<Paste>, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18