On Wed, 12 Mar 2025, Andrew Randrianasulu wrote:
> ---quote from user manual ---
>
> 2.1.1.4 Processor ID Register (PIR)
> The Processor Identification Register (PIR) is a 32-bit register that
> holds a processor identification tag. In the
> 970MP processing unit, this tag is in the three least-significant bits
> (29:31). The least-significant bit of the
> processor identification tag (PID) is hardwired to ‘0’ for PU0 and to
> ‘1’ for PU1. This tag is used to tag bus
> transactions and to differentiate processors in multiprocessor
> systems. The PIR is a read-only register. The
> format of the register is as follows:
>
> 0:28—Reserved (read as zeros)
> 29:31 PID3-bit processor ID value (least-significant bit hardwired to
> differentiate PU0 and PU1)
>
>
> During power-on reset, PID is set to a unique value for each processor
> in a multi processor system.
>
> =====
>
> 7.2.2.4 Processor ID (PROCID[0:1])–Input
> The 2-bit processor ID is used to assign unique IDs to the two 970MP
> processing units in a system that can
> have up to eight processors. The PROCID signals are sampled during
> power-on reset, and the 2-bit value is
> placed in the second and third lowest-order bits of the Processor ID
> Register (PIR) of each processing unit.
> The lowest-order PIR bit is hardwired to a '0' for PU0 and to '1' for PU1.
> Timing: These signals should be permanently tied to VDD or GND, as
> appropriate for the required ID value.
>
> === quote end ===
This suggests that at least on G5 it's strapped in hardware by wiring the
chip pins so each CPU has a different ID. The G4 could write it from
software but maybe it doesn't do that and sets it by hardware pins as
well. In any case, OpenBIOS does not write it but would set the reg
property based on it so probably it should be set in QEMU when creating
the CPUs. Then the part of the OpenBIOS patch that comments out the call
to set reg property based on pir and the part that sets the reg property
later can be dropped and thus the patch simplified (need less changes to
OpenBIOS).
To set PIR in QEMU look at what other machines do. By searching for PIR in
hw/ppc I've found:
hw/ppc/spapr_cpu_core.c::spapr_realize_vcpu()
...
env->spr_cb[SPR_PIR].default_value = cs->cpu_index;
hw/ppc/e500.c::ppce500_init()
for (i = 0; i < smp_cpus; i++) {
...
env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
The SPR number is different on e500 but the code is more similar to mac99
so in mac99 I think we should do what e500 does but use SPR_PIR instead of
SPR_BOOKE_PIR. What I'm not sure about if the cpu_reset in the kick
function would undo this but since it sets the default_value maybe that
means it would reset to this value so it should work. There's a -d
cpu_reset option to dump registers on cpu_reset but I think that shows
values before reset. You can try updating the patches accordingly (add a
line to QEMU as above and undo part of the openbios patch that should no
longer be needed)
I removed commenting out pir property from openbios patch but sadly it still does not work with g3 machine :(
and test if that works any better. Even if it does not
fix anything it would be cleaner so one step towards upstreaming. I don't
plan to do anything with this, one of you should be able to do this as an
excercise.
> this is from
>
> IBM PowerPC 970MP RISC Microprocessor
> User’s Manual
> Version 2.3
>
> filename DSASW0048145.pdf from DatasheetArchive
> https://datasheet.datasheetarchive.com/originals/library/Datasheets-SW3/DSASW0048145.pdf
>
> I wonder if qemu ppc wiki page already contain those links ?
Probably not as that's more user oriented.
Regards,
BALATON Zoltan