I think I found definition of PIR on 970MP

[Andrew Randrianasulu]

---quote from  user manual ---

2.1.1.4 Processor ID Register (PIR)
The Processor Identification Register (PIR) is a 32-bit register that
holds a processor identification tag. In the
970MP processing unit, this tag is in the three least-significant bits
(29:31). The least-significant bit of the
processor identification tag (PID) is hardwired to ‘0’ for PU0 and to
‘1’ for PU1. This tag is used to tag bus
transactions and to differentiate processors in multiprocessor
systems. The PIR is a read-only register. The
format of the register is as follows:

0:28—Reserved (read as zeros)
29:31 PID3-bit processor ID value (least-significant bit hardwired to
differentiate PU0 and PU1)


During power-on reset, PID is set to a unique value for each processor
in a multi processor system.

=====

7.2.2.4 Processor ID (PROCID[0:1])–Input
The 2-bit processor ID is used to assign unique IDs to the two 970MP
processing units in a system that can
have up to eight processors. The PROCID signals are sampled during
power-on reset, and the 2-bit value is
placed in the second and third lowest-order bits of the Processor ID
Register (PIR) of each processing unit.
The lowest-order PIR bit is hardwired to a '0' for PU0 and to '1' for PU1.
Timing: These signals should be permanently tied to VDD or GND, as
appropriate for the required ID value.

=== quote end ===

this is from

IBM PowerPC 970MP RISC Microprocessor
User’s Manual
Version 2.3

filename DSASW0048145.pdf from DatasheetArchive
https://datasheet.datasheetarchive.com/originals/library/Datasheets-SW3/DSASW0048145.pdf

I wonder if qemu ppc wiki page already contain those links ?