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[RFC PATCH 6/7] target/ppc: Implemented pmxvf*ger*
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From: |
Lucas Mateus Castro(alqotel) |
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Subject: |
[RFC PATCH 6/7] target/ppc: Implemented pmxvf*ger* |
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Date: |
Tue, 26 Apr 2022 09:50:27 -0300 |
From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
pmxvf16ger2: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update)
pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Negative accumulate
pmxvf16ger2np: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Positive accumulate
pmxvf16ger2pn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Positive multiply, Negative accumulate
pmxvf16ger2pp: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Positive multiply, Positive accumulate
pmxvf32ger: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update)
pmxvf32gernn: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Negative multiply, Negative accumulate
pmxvf32gernp: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Negative multiply, Positive accumulate
pmxvf32gerpn: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Positive multiply, Negative accumulate
pmxvf32gerpp: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Positive multiply, Positive accumulate
pmxvf64ger: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update)
pmxvf64gernn: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Negative multiply, Negative accumulate
pmxvf64gernp: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Negative multiply, Positive accumulate
pmxvf64gerpn: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Positive multiply, Negative accumulate
pmxvf64gerpp: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
target/ppc/insn64.decode | 39 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 33 ++++++++++++++++++++++++
2 files changed, 72 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 18915f1977..bc5e4dfe1a 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -73,10 +73,16 @@
%xx3_xa 2:1 16:5
%xx3_xb 1:1 11:5
%xx3_at 23:3 !function=times_4
+%xx3_xa_pair 2:1 17:4 !function=times_2
@MMIRR_XX3 ...... .. .... .. . . ........ xmsk:4 ymsk:4 \
...... ... .. ..... ..... ........ ... \
&MMIRR_XX3 xa=%xx3_xa xb=%xx3_xb xt=%xx3_at
+&MMIRR_XX3_NO_P xa xb xt xmsk ymsk
+@MMIRR_XX3_NO_P ...... .. .... .. . . ........ xmsk:4 .... \
+ ...... ... .. ..... ..... ........ ... \
+ &MMIRR_XX3_NO_P xb=%xx3_xb xt=%xx3_at
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -145,6 +151,39 @@ PMXVI16GER2S 000001 11 1001 -- - - pmsk:2 ------
........ \
PMXVI16GER2SPP 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 00101010 ..- @MMIRR_XX3
+PMXVF16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 00010011 ..- @MMIRR_XX3
+PMXVF16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 00010010 ..- @MMIRR_XX3
+PMXVF16GER2PN 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 10010010 ..- @MMIRR_XX3
+PMXVF16GER2NP 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 01010010 ..- @MMIRR_XX3
+PMXVF16GER2NN 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 11010010 ..- @MMIRR_XX3
+
+PMXVF32GER 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 00011011 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+PMXVF32GERPP 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 00011010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+PMXVF32GERPN 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 10011010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+PMXVF32GERNP 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 01011010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+PMXVF32GERNN 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 11011010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+
+PMXVF64GER 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 00111011 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+PMXVF64GERPP 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 00111010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+PMXVF64GERPN 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 10111010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+PMXVF64GERNP 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 01111010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+PMXVF64GERNN 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 11111010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+
### Prefixed No-operation Instruction
@PNOP 000001 11 0000-- 000000000000000000 \
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 9285e27159..06f5c1220d 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2867,6 +2867,22 @@ static bool do_ger_MMIRR_XX3(DisasContext *ctx,
arg_MMIRR_XX3 *a, uint32_t op,
return true;
}
+
+static bool do_ger_MMIRR_XX3_NO_PMSK(DisasContext *ctx, arg_MMIRR_XX3_NO_P *a,
+ int op_flag, void (*helper)(TCGv_env,
+ TCGv_i32, TCGv_i32, TCGv_i32,
+ TCGv_i32, TCGv_i32))
+{
+ arg_MMIRR_XX3 x;
+ x.xa = a->xa;
+ x.xb = a->xb;
+ x.xt = a->xt;
+ x.pmsk = 0x1;
+ x.ymsk = a->ymsk;
+ x.xmsk = a->xmsk;
+ return do_ger_MMIRR_XX3(ctx, &x, op_flag, helper);
+}
+
static bool do_ger_XX3(DisasContext *ctx, arg_XX3 *a, uint32_t op_flags,
void (*helper)(TCGv_env, TCGv_i32, TCGv_i32,
TCGv_i32, TCGv_i32, TCGv_i32))
@@ -2935,6 +2951,23 @@ TRANS(XVF64GERPN, do_ger_XX3, GER_PN,
gen_helper_XVF64GER)
TRANS(XVF64GERNP, do_ger_XX3, GER_NP, gen_helper_XVF64GER)
TRANS(XVF64GERNN, do_ger_XX3, GER_NN, gen_helper_XVF64GER)
+TRANS64(PMXVF16GER2, do_ger_MMIRR_XX3, GER_NOP, gen_helper_XVF16GER2)
+TRANS64(PMXVF16GER2PP, do_ger_MMIRR_XX3, GER_PP, gen_helper_XVF16GER2)
+TRANS64(PMXVF16GER2PN, do_ger_MMIRR_XX3, GER_PN, gen_helper_XVF16GER2)
+TRANS64(PMXVF16GER2NP, do_ger_MMIRR_XX3, GER_NP, gen_helper_XVF16GER2)
+TRANS64(PMXVF16GER2NN, do_ger_MMIRR_XX3, GER_NN, gen_helper_XVF16GER2)
+
+TRANS64(PMXVF32GER, do_ger_MMIRR_XX3_NO_PMSK, GER_NOP, gen_helper_XVF32GER)
+TRANS64(PMXVF32GERPP, do_ger_MMIRR_XX3_NO_PMSK, GER_PP, gen_helper_XVF32GER)
+TRANS64(PMXVF32GERPN, do_ger_MMIRR_XX3_NO_PMSK, GER_PN, gen_helper_XVF32GER)
+TRANS64(PMXVF32GERNP, do_ger_MMIRR_XX3_NO_PMSK, GER_NP, gen_helper_XVF32GER)
+TRANS64(PMXVF32GERNN, do_ger_MMIRR_XX3_NO_PMSK, GER_NN, gen_helper_XVF32GER)
+
+TRANS64(PMXVF64GER, do_ger_MMIRR_XX3_NO_PMSK, GER_NOP, gen_helper_XVF64GER)
+TRANS64(PMXVF64GERPP, do_ger_MMIRR_XX3_NO_PMSK, GER_PP, gen_helper_XVF64GER)
+TRANS64(PMXVF64GERPN, do_ger_MMIRR_XX3_NO_PMSK, GER_PN, gen_helper_XVF64GER)
+TRANS64(PMXVF64GERNP, do_ger_MMIRR_XX3_NO_PMSK, GER_NP, gen_helper_XVF64GER)
+TRANS64(PMXVF64GERNN, do_ger_MMIRR_XX3_NO_PMSK, GER_NN, gen_helper_XVF64GER)
#undef GER_NOP
#undef GER_PP
--
2.31.1
- Re: [RFC PATCH 2/7] target/ppc: Implemented xvi*ger* instructions, (continued)
[RFC PATCH 3/7] target/ppc: Implemented pmxvi*ger* instructions, Lucas Mateus Castro(alqotel), 2022/04/26
[RFC PATCH 4/7] target/ppc: Implemented xvf*ger*, Lucas Mateus Castro(alqotel), 2022/04/26
[RFC PATCH 5/7] target/ppc: Implemented xvf16ger*, Lucas Mateus Castro(alqotel), 2022/04/26
[RFC PATCH 6/7] target/ppc: Implemented pmxvf*ger*,
Lucas Mateus Castro(alqotel) <=
[RFC PATCH 7/7] target/ppc: Implemented [pm]xvbf16ger2*, Lucas Mateus Castro(alqotel), 2022/04/26
Re: [RFC PATCH 0/7] VSX MMA Implementation, Joel Stanley, 2022/04/27
Re: [RFC PATCH 0/7] VSX MMA Implementation, Lucas Mateus Martins Araujo e Castro, 2022/04/28