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Re: [PATCH v2] target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli f

From: Richard Henderson
Subject: Re: [PATCH v2] target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32
Date: Tue, 20 Jul 2021 05:33:17 -1000
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 7/20/21 3:55 AM, matheus.ferst@eldorado.org.br wrote:
From: Matheus Ferst<matheus.ferst@eldorado.org.br>

In commit 8f0a4b6a9b, we started to require L=0 for ppc32 to match what
The Programming Environments Manual say:

"For 32-bit implementations, the L field must be cleared, otherwise
the instruction form is invalid."

The stricter behavior, however, broke AROS boot on sam460ex, which is a
regression from 6.0. This patch partially reverts the change, raising
the exception only for CPUs known to require L=0 (e500 and e500mc) and
logging a guest error for other cases.

Both behaviors are acceptable by the PowerISA, which allows "the system
illegal instruction error handler to be invoked or yield boundedly
undefined results."

Reported-by: BALATON Zoltan<balaton@eik.bme.hu>
Fixes: 8f0a4b6a9b ("target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree")
Tested-by: BALATON Zoltan<balaton@eik.bme.hu>
Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
  target/ppc/translate/fixedpoint-impl.c.inc | 58 +++++++++++++++++++++-
  1 file changed, 56 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


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