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[Qemu-ppc] [PULL 29/60] ppc/xive: activate HV support
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 29/60] ppc/xive: activate HV support |
Date: |
Sun, 10 Mar 2019 19:26:32 +1100 |
From: Cédric Le Goater <address@hidden>
The NSR register of the HV ring has a different, although similar, bit
layout. TM_QW3_NSR_HE_PHYS bit should now be raised when the
Hypervisor interrupt line is signaled. Other bits TM_QW3_NSR_HE_POOL
and TM_QW3_NSR_HE_LSI are not modeled. LSI are for special interrupts
reserved for HW bringup and the POOL bit is used when signaling a
group of VPs. This is not currently implemented in Linux but it is in
pHyp.
The most important special commands on the HV TIMA page are added to
let the core manage interrupts : acking and changing the CPU priority.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/xive.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 54 insertions(+), 3 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 7d7992c0ce..a0b87001da 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -54,6 +54,8 @@ static uint8_t exception_mask(uint8_t ring)
switch (ring) {
case TM_QW1_OS:
return TM_QW1_NSR_EO;
+ case TM_QW3_HV_PHYS:
+ return TM_QW3_NSR_HE;
default:
g_assert_not_reached();
}
@@ -88,7 +90,16 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring)
uint8_t *regs = &tctx->regs[ring];
if (regs[TM_PIPR] < regs[TM_CPPR]) {
- regs[TM_NSR] |= exception_mask(ring);
+ switch (ring) {
+ case TM_QW1_OS:
+ regs[TM_NSR] |= TM_QW1_NSR_EO;
+ break;
+ case TM_QW3_HV_PHYS:
+ regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6);
+ break;
+ default:
+ g_assert_not_reached();
+ }
qemu_irq_raise(tctx->output);
}
}
@@ -109,6 +120,38 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t
ring, uint8_t cppr)
* XIVE Thread Interrupt Management Area (TIMA)
*/
+static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
+}
+
+static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned
size)
+{
+ return xive_tctx_accept(tctx, TM_QW3_HV_PHYS);
+}
+
+static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
+ unsigned size)
+{
+ uint64_t ret;
+
+ ret = tctx->regs[TM_QW2_HV_POOL + TM_WORD2] & TM_QW2W2_POOL_CAM;
+ tctx->regs[TM_QW2_HV_POOL + TM_WORD2] &= ~TM_QW2W2_POOL_CAM;
+ return ret;
+}
+
+static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff;
+}
+
+static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size)
+{
+ return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff;
+}
+
/*
* Define an access map for each page of the TIMA that we will use in
* the memory region ops to filter values when doing loads and stores
@@ -288,10 +331,16 @@ static const XiveTmOp xive_tm_operations[] = {
* effects
*/
{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL },
+ { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL
},
+ { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL },
+ { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll },
/* MMIOs above 2K : special operations with side effects */
{ XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg },
{ XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL
},
+ { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg },
+ { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx },
+ { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx },
};
static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool
write)
@@ -323,7 +372,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset,
uint64_t value,
const XiveTmOp *xto;
/*
- * TODO: check V bit in Q[0-3]W2, check PTER bit associated with CPU
+ * TODO: check V bit in Q[0-3]W2
*/
/*
@@ -360,7 +409,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset,
unsigned size)
const XiveTmOp *xto;
/*
- * TODO: check V bit in Q[0-3]W2, check PTER bit associated with CPU
+ * TODO: check V bit in Q[0-3]W2
*/
/*
@@ -472,6 +521,8 @@ static void xive_tctx_reset(void *dev)
*/
tctx->regs[TM_QW1_OS + TM_PIPR] =
ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);
+ tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =
+ ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
}
static void xive_tctx_realize(DeviceState *dev, Error **errp)
--
2.20.1
- [Qemu-ppc] [PULL 09/60] target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS, (continued)
- [Qemu-ppc] [PULL 09/60] target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 11/60] target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 12/60] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 14/60] target/ppc: Move handling of hardware breakpoints to a separate function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 10/60] target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 18/60] spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 06/60] target/ppc: Implement large decrementer support for TCG, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 22/60] ppc: externalize ppc_get_vcpu_by_pir(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 21/60] ppc/xive: hardwire the Physical CAM line of the thread context, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 15/60] target/ppc: Refactor kvm_handle_debug, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 29/60] ppc/xive: activate HV support,
David Gibson <=
- [Qemu-ppc] [PULL 19/60] target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 17/60] target/ppc/spapr: Clear partition table entry when allocating hash table, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 25/60] ppc/pnv: change the CPU machine_data presenter type to Object *, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 20/60] PPC: E500: Add FSL I2C controller and integrate RTC with it, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 31/60] ppc/pnv: psi: add a PSIHB_REG macro, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 41/60] mac_oldworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 32/60] ppc/pnv: psi: add a reset handler, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 24/60] ppc/pnv: export the xive_router_notify() routine, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 30/60] ppc/pnv: fix logging primitives using Ox, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 23/60] ppc/xive: export the TIMA memory accessors, David Gibson, 2019/03/10