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Re: [Qemu-ppc] [PATCH 17/34] target/ppc: convert VMX logical instruction
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 17/34] target/ppc: convert VMX logical instructions to use vector operations |
Date: |
Wed, 19 Dec 2018 17:29:25 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Dec 17, 2018 at 10:38:54PM -0800, Richard Henderson wrote:
> From: Mark Cave-Ayland <address@hidden>
>
> Signed-off-by: Mark Cave-Ayland <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>
Acked-by: David Gibson <address@hidden>
> Message-Id: <address@hidden>
> ---
> target/ppc/translate.c | 1 +
> target/ppc/translate/vmx-impl.inc.c | 63 ++++++++++++++++-------------
> 2 files changed, 37 insertions(+), 27 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 8e89aec14d..1b61bfa093 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -24,6 +24,7 @@
> #include "disas/disas.h"
> #include "exec/exec-all.h"
> #include "tcg-op.h"
> +#include "tcg-op-gvec.h"
> #include "qemu/host-utils.h"
> #include "exec/cpu_ldst.h"
>
> diff --git a/target/ppc/translate/vmx-impl.inc.c
> b/target/ppc/translate/vmx-impl.inc.c
> index 75d2b2280f..c13828a09d 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -262,41 +262,50 @@ GEN_VX_VMUL10(vmul10euq, 1, 0);
> GEN_VX_VMUL10(vmul10cuq, 0, 1);
> GEN_VX_VMUL10(vmul10ecuq, 1, 1);
>
> -/* Logical operations */
> -#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
> -static void glue(gen_, name)(DisasContext *ctx)
> \
> +#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
> +static void glue(gen_, name)(DisasContext *ctx) \
> { \
> - TCGv_i64 t0 = tcg_temp_new_i64(); \
> - TCGv_i64 t1 = tcg_temp_new_i64(); \
> - TCGv_i64 avr = tcg_temp_new_i64(); \
> - \
> if (unlikely(!ctx->altivec_enabled)) { \
> gen_exception(ctx, POWERPC_EXCP_VPU); \
> return; \
> } \
> - get_avr64(t0, rA(ctx->opcode), true); \
> - get_avr64(t1, rB(ctx->opcode), true); \
> - tcg_op(avr, t0, t1); \
> - set_avr64(rD(ctx->opcode), avr, true); \
> \
> - get_avr64(t0, rA(ctx->opcode), false); \
> - get_avr64(t1, rB(ctx->opcode), false); \
> - tcg_op(avr, t0, t1); \
> - set_avr64(rD(ctx->opcode), avr, false); \
> - \
> - tcg_temp_free_i64(t0); \
> - tcg_temp_free_i64(t1); \
> - tcg_temp_free_i64(avr); \
> + tcg_op(vece, \
> + avr64_offset(rD(ctx->opcode), true), \
> + avr64_offset(rA(ctx->opcode), true), \
> + avr64_offset(rB(ctx->opcode), true), \
> + 16, 16); \
> }
>
> -GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
> -GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
> -GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
> -GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
> -GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
> -GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
> -GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
> -GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
> +#define GEN_VXFORM_VN(name, vece, tcg_op, opc2, opc3) \
> +static void glue(gen_, name)(DisasContext *ctx) \
> +{ \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + \
> + tcg_op(vece, \
> + avr64_offset(rD(ctx->opcode), true), \
> + avr64_offset(rA(ctx->opcode), true), \
> + avr64_offset(rB(ctx->opcode), true), \
> + 16, 16); \
> + \
> + tcg_gen_gvec_not(vece, \
> + avr64_offset(rD(ctx->opcode), true), \
> + avr64_offset(rD(ctx->opcode), true), \
> + 16, 16); \
> +}
> +
> +/* Logical operations */
> +GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
> +GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
> +GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
> +GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
> +GEN_VXFORM_VN(vnor, MO_64, tcg_gen_gvec_or, 2, 20);
> +GEN_VXFORM_VN(veqv, MO_64, tcg_gen_gvec_xor, 2, 26);
> +GEN_VXFORM_VN(vnand, MO_64, tcg_gen_gvec_and, 2, 22);
> +GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
>
> #define GEN_VXFORM(name, opc2, opc3) \
> static void glue(gen_, name)(DisasContext *ctx)
> \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [PATCH 29/34] target/ppc: Add helper_mfvscr, (continued)
- [Qemu-ppc] [PATCH 23/34] target/ppc: convert xxspltib to vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 10/34] target/arm: Use vector minmax expanders for aarch32, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 19/34] target/ppc: convert vspltis[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 26/34] target/ppc: Pass integer to helper_mtvscr, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 07/34] tcg: Add opcodes for vector minmax arithmetic, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 17/34] target/ppc: convert VMX logical instructions to use vector operations, Richard Henderson, 2018/12/18
- Re: [Qemu-ppc] [PATCH 17/34] target/ppc: convert VMX logical instructions to use vector operations,
David Gibson <=
- [Qemu-ppc] [PATCH 24/34] target/ppc: convert xxspltw to vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 11/34] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 09/34] target/arm: Use vector minmax expanders for aarch64, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 28/34] target/ppc: Remove vscr_nj and vscr_sat, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 33/34] target/ppc: convert vadd*s and vsub*s to vector operations, Richard Henderson, 2018/12/18