[Qemu-ppc] [PATCH v9 0/7] ppc: support for the XIVE interrupt controller (POWER9)

[Cédric Le Goater]

Hello,

Here is the version 9 of the QEMU models adding support for the XIVE
interrupt controller to the sPAPR machine, under TCG only. 

The 'dual' machine, supporting both interrupt modes, is nearly complete,
only remains the question on the qirq array, which will be addressed
in early 2019 with the support for KVM.

Thanks,

C.

Changes in v9 (sPAPR only) :

 - fixed compile breakage on windows
 - reworked XIVE capability in ibm,arch-vec-5-platform-support 
 - fixed default CPU type on 3.1 machines
 - updated MAINTAINERS file
 
* GitHub trees
 
QEMU sPAPR:

  https://github.com/legoater/qemu/commits/xive-v9-4.0
  
QEMU PowerNV:

  https://github.com/legoater/qemu/commits/powernv-3.1

Linux/KVM:

  https://github.com/legoater/linux/commits/xive-4.20

OPAL:

  https://github.com/legoater/skiboot/commits/xive

Cédric Le Goater (7):
  target/ppc: fix the PPC_BIT definitions
  target/ppc: replace __builtin_ffssl() by the equivalent ctz routines
  spapr/xive: fix compilation breakage on windows
  spapr: add an extra OV5 field to the sPAPR IRQ backend
  spapr: introduce an 'ic-mode' machine option
  spapr: change default CPU type to POWER9
  MAINTAINERS: PPC: add a XIVE section

 include/hw/ppc/spapr.h     |  7 ++++
 include/hw/ppc/spapr_irq.h |  1 +
 target/ppc/cpu.h           | 21 +++++-----
 hw/intc/spapr_xive.c       | 46 +++++++++++++---------
 hw/ppc/spapr.c             | 80 ++++++++++++++++++++++++++++++++------
 hw/ppc/spapr_cpu_core.c    |  3 +-
 hw/ppc/spapr_irq.c         | 37 +++++++-----------
 MAINTAINERS                |  8 ++++
 8 files changed, 138 insertions(+), 65 deletions(-)

-- 
2.17.2