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[Qemu-ppc] [PATCH v9 3/7] spapr/xive: fix compilation breakage on window
|
From: |
Cédric Le Goater |
|
Subject: |
[Qemu-ppc] [PATCH v9 3/7] spapr/xive: fix compilation breakage on windows |
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Date: |
Mon, 17 Dec 2018 23:34:41 +0100 |
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++-----------------
1 file changed, 28 insertions(+), 18 deletions(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index aaa5865c4080..3ceabe668b16 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -589,12 +589,14 @@ static target_ulong h_int_get_source_info(PowerPCCPU *cpu,
}
if (lisn >= xive->nr_irqs) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
if (!xive_eas_is_valid(&xive->eat[lisn])) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
@@ -701,13 +703,15 @@ static target_ulong h_int_set_source_config(PowerPCCPU
*cpu,
}
if (lisn >= xive->nr_irqs) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
eas = xive->eat[lisn];
if (!xive_eas_is_valid(&eas)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
@@ -724,8 +728,8 @@ static target_ulong h_int_set_source_config(PowerPCCPU *cpu,
}
if (spapr_xive_priority_is_reserved(priority)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
- priority);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+ " is reserved\n", priority);
return H_P4;
}
@@ -793,13 +797,15 @@ static target_ulong h_int_get_source_config(PowerPCCPU
*cpu,
}
if (lisn >= xive->nr_irqs) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
eas = xive->eat[lisn];
if (!xive_eas_is_valid(&eas)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
@@ -870,8 +876,8 @@ static target_ulong h_int_get_queue_info(PowerPCCPU *cpu,
*/
if (spapr_xive_priority_is_reserved(priority)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
- priority);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+ " is reserved\n", priority);
return H_P3;
}
@@ -956,8 +962,8 @@ static target_ulong h_int_set_queue_config(PowerPCCPU *cpu,
*/
if (spapr_xive_priority_is_reserved(priority)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
- priority);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+ " is reserved\n", priority);
return H_P3;
}
@@ -1102,8 +1108,8 @@ static target_ulong h_int_get_queue_config(PowerPCCPU
*cpu,
*/
if (spapr_xive_priority_is_reserved(priority)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
- priority);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+ " is reserved\n", priority);
return H_P3;
}
@@ -1268,13 +1274,15 @@ static target_ulong h_int_esb(PowerPCCPU *cpu,
}
if (lisn >= xive->nr_irqs) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
eas = xive->eat[lisn];
if (!xive_eas_is_valid(&eas)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
@@ -1330,13 +1338,15 @@ static target_ulong h_int_sync(PowerPCCPU *cpu,
}
if (lisn >= xive->nr_irqs) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
eas = xive->eat[lisn];
if (!xive_eas_is_valid(&eas)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
+ lisn);
return H_P2;
}
--
2.17.2
- [Qemu-ppc] [PATCH v9 0/7] ppc: support for the XIVE interrupt controller (POWER9), Cédric Le Goater, 2018/12/17
- [Qemu-ppc] [PATCH v9 3/7] spapr/xive: fix compilation breakage on windows,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v9 4/7] spapr: add an extra OV5 field to the sPAPR IRQ backend, Cédric Le Goater, 2018/12/17
- [Qemu-ppc] [PATCH v9 5/7] spapr: introduce an 'ic-mode' machine option, Cédric Le Goater, 2018/12/17
- [Qemu-ppc] [PATCH v9 6/7] spapr: change default CPU type to POWER9, Cédric Le Goater, 2018/12/17
- [Qemu-ppc] [PATCH v9 7/7] MAINTAINERS: PPC: add a XIVE section, Cédric Le Goater, 2018/12/17
- Re: [Qemu-ppc] [PATCH v9 0/7] ppc: support for the XIVE interrupt controller (POWER9), David Gibson, 2018/12/17