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Re: [Qemu-ppc] [RFC PATCH 0/6] target/ppc: convert VMX instructions to u

From: David Gibson
Subject: Re: [Qemu-ppc] [RFC PATCH 0/6] target/ppc: convert VMX instructions to use TCG vector operations
Date: Mon, 10 Dec 2018 13:59:43 +1100
User-agent: Mutt/1.10.1 (2018-07-13)

On Mon, Dec 10, 2018 at 01:33:53AM +0100, BALATON Zoltan wrote:
> On Fri, 7 Dec 2018, Mark Cave-Ayland wrote:
> > This patchset is an attempt at trying to improve the VMX (Altivec) 
> > instruction
> > performance by making use of the new TCG vector operations where possible.
> This is very welcome, thanks for doing this.
> > In order to use TCG vector operations, the registers must be accessible 
> > from cpu_env
> > whilst currently they are accessed via arrays of static TCG globals. 
> > Patches 1-3
> > are therefore mechanical patches which introduce access helpers for FPR, 
> > AVR and VSR
> > registers using the supplied TCGv_i64 parameter.
> Have you tried some benchmarks or tests to measure the impact of these
> changes? I've tried the (very unscientific) benchmarks I've written about
> before here:
> http://lists.nongnu.org/archive/html/qemu-ppc/2018-07/msg00261.html
> (which seem to use AltiVec/VMX instructions but not sure which) on mac99
> with MorphOS and I could not see any performance increase. I haven't run
> enough tests but results with or without this series on master were mostly
> the same within a few percents, and sometimes even seen lower performance
> with these patches than without. I haven't tried to find out why (no time
> for that now) so can't really draw any conclusions from this. I'm also not
> sure if I've actually tested what you've changed or these use instructions
> that your patches don't optimise yet, or the changes I've seen were just
> normal changes between runs; but I wonder if the increased number of
> temporaries could result in lower performance in some cases?

What was your host machine.  IIUC this change will only improve
performance if the host tcg backend is able to implement TCG vector
ops in terms of vector ops on the host.

In addition, this series only converts a subset of the integer and
logical vector instructions.  If your testcase is mostly floating
point (vectored or otherwise), it will still be softfloat and so not
see any speedup.

David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!

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