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Re: [Qemu-ppc] [PATCH v5 21/36] spapr: extend the sPAPR IRQ backend for
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v5 21/36] spapr: extend the sPAPR IRQ backend for XICS migration |
Date: |
Wed, 28 Nov 2018 16:54:04 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Fri, Nov 16, 2018 at 11:57:14AM +0100, Cédric Le Goater wrote:
> Introduce a new sPAPR IRQ handler to handle resend after migration
> when the machine is using a KVM XICS interrupt controller model.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> include/hw/ppc/spapr_irq.h | 2 ++
> hw/ppc/spapr.c | 13 +++++--------
> hw/ppc/spapr_irq.c | 27 +++++++++++++++++++++++++++
> 3 files changed, 34 insertions(+), 8 deletions(-)
>
> diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
> index b299dd794bff..4e36c0984e1a 100644
> --- a/include/hw/ppc/spapr_irq.h
> +++ b/include/hw/ppc/spapr_irq.h
> @@ -45,6 +45,7 @@ typedef struct sPAPRIrq {
> void *fdt, uint32_t phandle);
> Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu,
> Error **errp);
> + int (*post_load)(sPAPRMachineState *spapr, int version_id);
> } sPAPRIrq;
>
> extern sPAPRIrq spapr_irq_xics;
> @@ -55,6 +56,7 @@ void spapr_irq_init(sPAPRMachineState *spapr, int
> nr_servers, Error **errp);
> int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error
> **errp);
> void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
> qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
> +int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id);
>
> /*
> * XICS legacy routines
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 8fbb743769db..f9cf2debff5a 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1738,14 +1738,6 @@ static int spapr_post_load(void *opaque, int
> version_id)
> return err;
> }
>
> - if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
> - CPUState *cs;
> - CPU_FOREACH(cs) {
> - PowerPCCPU *cpu = POWERPC_CPU(cs);
> - icp_resend(ICP(cpu->intc));
> - }
> - }
> -
> /* In earlier versions, there was no separate qdev for the PAPR
> * RTC, so the RTC offset was stored directly in sPAPREnvironment.
> * So when migrating from those versions, poke the incoming offset
> @@ -1766,6 +1758,11 @@ static int spapr_post_load(void *opaque, int
> version_id)
> }
> }
>
> + err = spapr_irq_post_load(spapr, version_id);
> + if (err) {
> + return err;
> + }
> +
> return err;
> }
>
> diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
> index f6e9e44d4cf9..33dd5da7d255 100644
> --- a/hw/ppc/spapr_irq.c
> +++ b/hw/ppc/spapr_irq.c
> @@ -203,6 +203,18 @@ static Object
> *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
> return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp);
> }
>
> +static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
> +{
> + if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
> + CPUState *cs;
> + CPU_FOREACH(cs) {
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + icp_resend(ICP(cpu->intc));
> + }
> + }
> + return 0;
> +}
> +
> #define SPAPR_IRQ_XICS_NR_IRQS 0x1000
> #define SPAPR_IRQ_XICS_NR_MSIS \
> (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
> @@ -219,6 +231,7 @@ sPAPRIrq spapr_irq_xics = {
> .print_info = spapr_irq_print_info_xics,
> .dt_populate = spapr_irq_dt_populate_xics,
> .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
> + .post_load = spapr_irq_post_load_xics,
> };
>
> /*
> @@ -331,6 +344,11 @@ static Object
> *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
> XIVE_ROUTER(spapr->xive), errp);
> }
>
> +static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
> +{
> + return 0;
> +}
> +
> /*
> * XIVE uses the full IRQ number space. Set it to 8K to be compatible
> * with XICS.
> @@ -351,6 +369,7 @@ sPAPRIrq spapr_irq_xive = {
> .print_info = spapr_irq_print_info_xive,
> .dt_populate = spapr_irq_dt_populate_xive,
> .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
> + .post_load = spapr_irq_post_load_xive,
> };
>
> /*
> @@ -389,6 +408,13 @@ qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
> return smc->irq->qirq(spapr, irq);
> }
>
> +int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
> +{
> + sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
> +
> + return smc->irq->post_load(spapr, version_id);
> +}
> +
> /*
> * XICS legacy routines - to deprecate one day
> */
> @@ -458,4 +484,5 @@ sPAPRIrq spapr_irq_xics_legacy = {
> .print_info = spapr_irq_print_info_xics,
> .dt_populate = spapr_irq_dt_populate_xics,
> .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
> + .post_load = spapr_irq_post_load_xics,
> };
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [PATCH v5 18/36] spapr: allocate the interrupt thread context under the CPU core, (continued)
[Qemu-ppc] [PATCH v5 21/36] spapr: extend the sPAPR IRQ backend for XICS migration, Cédric Le Goater, 2018/11/16
- Re: [Qemu-ppc] [PATCH v5 21/36] spapr: extend the sPAPR IRQ backend for XICS migration,
David Gibson <=
[Qemu-ppc] [PATCH v5 23/36] spapr/xive: add migration support for KVM, Cédric Le Goater, 2018/11/16
[Qemu-ppc] [PATCH v5 24/36] spapr: add a 'reset' method to the sPAPR IRQ backend, Cédric Le Goater, 2018/11/16
[Qemu-ppc] [PATCH v5 22/36] spapr/xive: add models for KVM support, Cédric Le Goater, 2018/11/16