Re: [Qemu-ppc] [PATCH v5 18/36] spapr: allocate the interrupt thread context under the CPU core

[David Gibson]

On Fri, Nov 16, 2018 at 11:57:11AM +0100, Cédric Le Goater wrote:
> Each interrupt mode has its own specific interrupt presenter object,
> that we store under the CPU object, one for XICS and one for XIVE.
> 
> Extend the sPAPR IRQ backend with a new handler to support them both.
> 
> Signed-off-by: Cédric Le Goater <address@hidden>

Reviewed-by: David Gibson <address@hidden>

> ---
>  include/hw/ppc/spapr.h     |  1 +
>  include/hw/ppc/spapr_irq.h |  2 ++
>  include/hw/ppc/xive.h      |  2 ++
>  hw/intc/xive.c             | 21 +++++++++++++++++++++
>  hw/ppc/spapr_cpu_core.c    |  5 ++---
>  hw/ppc/spapr_irq.c         | 17 +++++++++++++++++
>  6 files changed, 45 insertions(+), 3 deletions(-)
> 
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 8415faea7b82..f43ef69d61bc 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -177,6 +177,7 @@ struct sPAPRMachineState {
>      int32_t irq_map_nr;
>      unsigned long *irq_map;
>      sPAPRXive  *xive;
> +    const char *xive_tctx_type;
>  
>      bool cmd_line_caps[SPAPR_CAP_NUM];
>      sPAPRCapabilities def, eff, mig;
> diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
> index cfdc1f86e713..c3b4c38145eb 100644
> --- a/include/hw/ppc/spapr_irq.h
> +++ b/include/hw/ppc/spapr_irq.h
> @@ -42,6 +42,8 @@ typedef struct sPAPRIrq {
>      void (*print_info)(sPAPRMachineState *spapr, Monitor *mon);
>      void (*dt_populate)(sPAPRMachineState *spapr, uint32_t nr_servers,
>                          void *fdt, uint32_t phandle);
> +    Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu,
> +                               Error **errp);
>  } sPAPRIrq;
>  
>  extern sPAPRIrq spapr_irq_xics;
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index e6931ddaa83f..b74eb326dcd1 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -284,6 +284,8 @@ typedef struct XiveTCTX {
>  extern const MemoryRegionOps xive_tm_ops;
>  
>  void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
> +Object *xive_tctx_create(Object *cpu, const char *type, XiveRouter *xrtr,
> +                         Error **errp);
>  
>  static inline uint32_t xive_tctx_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
>  {
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index fc6ef5895e6d..7d921023e2ee 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -579,6 +579,27 @@ static const TypeInfo xive_tctx_info = {
>      .class_init    = xive_tctx_class_init,
>  };
>  
> +Object *xive_tctx_create(Object *cpu, const char *type, XiveRouter *xrtr,
> +                         Error **errp)
> +{
> +    Error *local_err = NULL;
> +    Object *obj;
> +
> +    obj = object_new(type);
> +    object_property_add_child(cpu, type, obj, &error_abort);
> +    object_unref(obj);
> +    object_property_add_const_link(obj, "cpu", cpu, &error_abort);
> +    object_property_add_const_link(obj, "xive", OBJECT(xrtr), &error_abort);
> +    object_property_set_bool(obj, true, "realized", &local_err);
> +    if (local_err) {
> +        object_unparent(obj);
> +        error_propagate(errp, local_err);
> +        return NULL;
> +    }
> +
> +    return obj;
> +}
> +
>  /*
>   * XIVE ESB helpers
>   */
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 2398ce62c0e7..1811cd48db90 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -11,7 +11,6 @@
>  #include "hw/ppc/spapr_cpu_core.h"
>  #include "target/ppc/cpu.h"
>  #include "hw/ppc/spapr.h"
> -#include "hw/ppc/xics.h" /* for icp_create() - to be removed */
>  #include "hw/boards.h"
>  #include "qapi/error.h"
>  #include "sysemu/cpus.h"
> @@ -215,6 +214,7 @@ static void spapr_cpu_core_unrealize(DeviceState *dev, 
> Error **errp)
>  static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>                                 sPAPRCPUCore *sc, Error **errp)
>  {
> +    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
>      CPUPPCState *env = &cpu->env;
>      CPUState *cs = CPU(cpu);
>      Error *local_err = NULL;
> @@ -233,8 +233,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, 
> sPAPRMachineState *spapr,
>      qemu_register_reset(spapr_cpu_reset, cpu);
>      spapr_cpu_reset(cpu);
>  
> -    cpu->intc = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
> -                           &local_err);
> +    cpu->intc = smc->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_err);
>      if (local_err) {
>          goto error_unregister;
>      }
> diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
> index d88a029d8c5c..253abc10e780 100644
> --- a/hw/ppc/spapr_irq.c
> +++ b/hw/ppc/spapr_irq.c
> @@ -197,6 +197,12 @@ static void spapr_irq_dt_populate_xics(sPAPRMachineState 
> *spapr,
>      spapr_dt_xics(nr_servers, fdt, phandle);
>  }
>  
> +static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
> +                                              Object *cpu, Error **errp)
> +{
> +    return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp);
> +}
> +
>  #define SPAPR_IRQ_XICS_NR_IRQS     0x1000
>  #define SPAPR_IRQ_XICS_NR_MSIS     \
>      (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
> @@ -211,6 +217,7 @@ sPAPRIrq spapr_irq_xics = {
>      .qirq        = spapr_qirq_xics,
>      .print_info  = spapr_irq_print_info_xics,
>      .dt_populate = spapr_irq_dt_populate_xics,
> +    .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
>  };
>  
>   /*
> @@ -267,6 +274,7 @@ static void spapr_irq_init_xive(sPAPRMachineState *spapr, 
> int nr_irqs,
>          return;
>      }
>  
> +    spapr->xive_tctx_type = TYPE_XIVE_TCTX;
>      spapr_xive_hcall_init(spapr);
>  }
>  
> @@ -315,6 +323,13 @@ static void spapr_irq_dt_populate_xive(sPAPRMachineState 
> *spapr,
>      spapr_dt_xive(spapr->xive, nr_servers, fdt, phandle);
>  }
>  
> +static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
> +                                              Object *cpu, Error **errp)
> +{
> +    return xive_tctx_create(cpu, spapr->xive_tctx_type,
> +                            XIVE_ROUTER(spapr->xive), errp);
> +}
> +
>  /*
>   * XIVE uses the full IRQ number space. Set it to 8K to be compatible
>   * with XICS.
> @@ -333,6 +348,7 @@ sPAPRIrq spapr_irq_xive = {
>      .qirq        = spapr_qirq_xive,
>      .print_info  = spapr_irq_print_info_xive,
>      .dt_populate = spapr_irq_dt_populate_xive,
> +    .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
>  };
>  
>  /*
> @@ -438,4 +454,5 @@ sPAPRIrq spapr_irq_xics_legacy = {
>      .qirq        = spapr_qirq_xics,
>      .print_info  = spapr_irq_print_info_xics,
>      .dt_populate = spapr_irq_dt_populate_xics,
> +    .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
>  };

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

signature.asc
Description: PGP signature