Re: [Qemu-ppc] [PATCH] target/ppc: Fix backwards migration of msr_mask

[Greg Kurz]

On Tue, 20 Mar 2018 13:23:19 +1100
David Gibson <address@hidden> wrote:

> 21b786f "PowerPC: Add TS bits into msr_mask" added the transaction states
> to msr_mask for recent POWER CPUs to allow correct migration of machines
> that are in certain interim transactional memory states.
> 
> This was correct, but unfortunately breaks backwards of pseries-2.7 and
> earlier machine types which (stupidly) transferred the msr_mask in the
> migration stream and failed if it wasn't equal on each end.
> 
> This works around the problem by masking out the new MSR bits in the
> compatibility code to send the msr_mask on old machine types.
> 
> Signed-off-by: David Gibson <address@hidden>
> ---

Reviewed-by: Greg Kurz <address@hidden>

and

Tested-by: Greg Kurz <address@hidden>

>  target/ppc/machine.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index e475206c6a..0634cdb295 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -190,7 +190,15 @@ static int cpu_pre_save(void *opaque)
>  
>      /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
>      if (cpu->pre_2_8_migration) {
> -        cpu->mig_msr_mask = env->msr_mask;
> +        /* Mask out bits that got added to msr_mask since the versions
> +         * which stupidly included it in the migration stream. */
> +        target_ulong metamask = 0
> +#if defined(TARGET_PPC64)
> +            | (1ULL << MSR_TS0)
> +            | (1ULL << MSR_TS1)
> +#endif
> +            ;
> +        cpu->mig_msr_mask = env->msr_mask & ~metamask;
>          cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
>          cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
>          cpu->mig_nb_BATs = env->nb_BATs;