[Qemu-ppc] [PATCH v4 08/15] target/ppc: update ca32 in arithmetic add

[Nikunj A Dadhania]

Adds routine to compute ca32 - gen_op_arith_compute_ca32

For 64-bit mode use the compute ca32 routine. While for 32-bit mode, CA
and CA32 will have same value.

Signed-off-by: Nikunj A Dadhania <address@hidden>
---
 target/ppc/translate.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5be1bb9..c98e708 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -799,6 +799,28 @@ static inline void gen_op_update_ca_legacy(TCGv ca)
     tcg_temp_free(t0);
 }
 
+static inline void gen_op_update_ca_isa300(TCGv ca, TCGv ca32)
+{
+    TCGv t0 = tcg_temp_new();
+
+    tcg_gen_movi_tl(t0, XER_CA | XER_CA32);
+    tcg_gen_andc_tl(cpu_xer, cpu_xer, t0);
+    tcg_gen_shli_tl(t0, ca, XER_CA_BIT);
+    tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
+    tcg_gen_shli_tl(t0, ca32, XER_CA32_BIT);
+    tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
+    tcg_temp_free(t0);
+}
+
+static inline void gen_op_update_ca(DisasContext *ctx, TCGv ca, TCGv ca32)
+{
+    if (is_isa300(ctx)) {
+        gen_op_update_ca_isa300(ca, ca32);
+    } else {
+        gen_op_update_ca_legacy(ca);
+    }
+}
+
 static inline void gen_op_update_ov_legacy(TCGv ov)
 {
     TCGv t1 = tcg_temp_new();
@@ -844,6 +866,23 @@ static inline void gen_op_arith_compute_ov(DisasContext 
*ctx, TCGv arg0,
     tcg_temp_free(ov);
 }
 
+static inline void gen_op_arith_compute_ca32(DisasContext *ctx, TCGv ca32,
+                                             TCGv res, TCGv arg0, TCGv arg1,
+                                             int sub)
+{
+    TCGv t0;
+
+    if (!is_isa300(ctx)) {
+        return;
+    }
+
+    t0 = tcg_temp_new();
+    tcg_gen_xor_tl(t0, arg0, arg1);
+    tcg_gen_xor_tl(t0, t0, res);
+    tcg_gen_extract_tl(ca32, t0, 32, 1);
+    tcg_temp_free(t0);
+}
+
 /* Common add function */
 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
                                     TCGv arg2, bool add_ca, bool compute_ca,
@@ -851,6 +890,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv 
ret, TCGv arg1,
 {
     TCGv t0 = ret;
     TCGv ca = tcg_temp_new();
+    TCGv ca32 = tcg_temp_new();
 
     if (compute_ca || compute_ov) {
         t0 = tcg_temp_new();
@@ -874,6 +914,9 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv 
ret, TCGv arg1,
             tcg_gen_xor_tl(ca, t0, t1);        /* bits changed w/ carry */
             tcg_temp_free(t1);
             tcg_gen_extract_tl(ca, ca, 32, 1);
+            if (is_isa300(ctx)) {
+                tcg_gen_mov_tl(ca32, ca);
+            }
         } else {
             TCGv zero = tcg_const_tl(0);
             if (add_ca) {
@@ -882,6 +925,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv 
ret, TCGv arg1,
             } else {
                 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
             }
+            gen_op_arith_compute_ca32(ctx, ca32, t0, arg1, arg2, 0);
             tcg_temp_free(zero);
         }
     } else {
@@ -895,7 +939,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv 
ret, TCGv arg1,
         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
     }
     if (compute_ca) {
-        gen_op_update_ca_legacy(ca);
+        gen_op_update_ca(ctx, ca, ca32);
     }
     if (unlikely(compute_rc0)) {
         gen_set_Rc0(ctx, t0);
@@ -906,6 +950,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv 
ret, TCGv arg1,
         tcg_temp_free(t0);
     }
     tcg_temp_free(ca);
+    tcg_temp_free(ca32);
 }
 /* Add functions with two operands */
 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
-- 
2.7.4