[Qemu-ppc] [PATCH v4 12/15] target/ppc: update OV/OV32 for divide operations

[Nikunj A Dadhania]

Add helper_update_ov_isa300() in the int_helper for updating the
overflow flags.

For Divide Word:
SO, OV, and OV32 bits reflects overflow of the 32-bit result

For Divide DoubleWord:
SO, OV, and OV32 bits reflects overflow of the 64-bit result

Signed-off-by: Nikunj A Dadhania <address@hidden>
---
 target/ppc/int_helper.c | 17 +++++++++++++++++
 target/ppc/translate.c  |  8 ++++----
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b0c3c2b..8cedce6 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -36,6 +36,23 @@ static inline void helper_update_ov_legacy(CPUPPCState *env, 
int ov)
     }
 }
 
+static inline void helper_update_ov_isa300(CPUPPCState *env, int ov, int ov32)
+{
+    env->xer = env->xer & ~(XER_OV | XER_OV32);
+    if (ov) {
+        env->xer |= XER_SO | XER_OV | XER_OV32;
+    }
+}
+
+static inline void helper_update_ov(CPUPPCState *env, int ov)
+{
+    if (is_isa300(env)) {
+        helper_update_ov_isa300(env, ov, ov);
+    } else {
+        helper_update_ov_legacy(env, ov);
+    }
+}
+
 static inline void helper_update_ca(CPUPPCState *env, int ca)
 {
     env->xer = env->xer & ~(XER_CA);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e1105e8..f7d37b0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1100,7 +1100,7 @@ static inline void gen_op_arith_divw(DisasContext *ctx, 
TCGv ret, TCGv arg1,
     if (compute_ov) {
         TCGv ov = tcg_temp_new();
         tcg_gen_extu_i32_tl(ov, t2);
-        gen_op_update_ov_legacy(ov);
+        gen_op_update_ov(ctx, ov, ov);
         tcg_temp_free(ov);
     }
     tcg_temp_free_i32(t0);
@@ -1171,7 +1171,7 @@ static inline void gen_op_arith_divd(DisasContext *ctx, 
TCGv ret, TCGv arg1,
         tcg_gen_divu_i64(ret, t0, t1);
     }
     if (compute_ov) {
-        gen_op_update_ov_legacy(t2);
+        gen_op_update_ov(ctx, t2, t2);
     }
     tcg_temp_free_i64(t0);
     tcg_temp_free_i64(t1);
@@ -1189,10 +1189,10 @@ static void glue(gen_, name)(DisasContext *ctx)
                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
                       sign, compute_ov);                                      \
 }
-/* divwu  divwu.  divwuo  divwuo.   */
+/* divdu  divdu.  divduo  divduo.   */
 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
-/* divw  divw.  divwo  divwo.   */
+/* divd  divd.  divdo  divdo.   */
 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
 
-- 
2.7.4