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Re: [Qemu-ppc] [PATCH v2 3/4] target-ppc: Implement bcdcfz. instruction
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v2 3/4] target-ppc: Implement bcdcfz. instruction |
Date: |
Mon, 31 Oct 2016 13:28:37 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Fri, Oct 28, 2016 at 03:18:03PM -0200, Jose Ricardo Ziviani wrote:
> bcdcfz. converts from Zoned numeric format to BCD. Zoned format uses
> a byte to represent a digit where the most significant nibble is 0x3
> or 0xf, depending on the preferred signal.
>
> Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Only a trivial fix, otherwise looks ok now (I wouldn't mention
something this small, except that the series will need a respin
anyway, so it might as well get fixed).
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 47
> +++++++++++++++++++++++++++++++++++++
> target-ppc/translate/vmx-impl.inc.c | 7 ++++--
> 3 files changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 53d1e7a..a9ac28b 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -373,6 +373,7 @@ DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
> DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
> DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
> DEF_HELPER_2(bcdctn, i32, avr, avr)
> +DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
>
> DEF_HELPER_2(xsadddp, void, env, i32)
> DEF_HELPER_2(xssubdp, void, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index a58ed30..19e6a3a 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2727,6 +2727,53 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b)
> return cr;
> }
>
> +uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
> +{
> + int i;
> + int j;
> + int cr = 0;
> + int invalid = 0;
> + int neq_flag = 0;
> + int zone_digit = 0;
> + int zone_lead = (ps) ? 0xF : 0x3;
No need to bracket ps here.
> + int digit = 0;
> + ppc_avr_t ret = { .u64 = { 0, 0 } };
> + int sgnb = b->u8[BCD_DIG_BYTE(0)] >> 4;
> +
> + if (unlikely((sgnb < 0xA) && ps)) {
> + invalid = 1;
> + }
> +
> + for (i = 0, j = 1; i < 31; i += 2, j++) {
> + zone_digit = (i) ? b->u8[BCD_DIG_BYTE(i)] >> 4 : zone_lead;
> + digit = b->u8[BCD_DIG_BYTE(i)] & 0xF;
> +
> + if (unlikely(zone_digit != zone_lead || digit > 0x9)) {
> + invalid = 1;
> + break;
> + }
> +
> + neq_flag += (digit != 0);
> + bcd_put_digit(&ret, digit, j);
> + }
> +
> + if ((ps && (sgnb == 0xB || sgnb == 0xD)) ||
> + (!ps && (sgnb & 0x4))) {
> + bcd_put_digit(&ret, BCD_NEG_PREF, 0);
> + cr = (neq_flag) ? 1 << CRF_LT : 1 << CRF_EQ;
> + } else {
> + bcd_put_digit(&ret, BCD_PLUS_PREF_1, 0);
> + cr = (neq_flag) ? 1 << CRF_GT : 1 << CRF_EQ;
> + }
> +
> + if (unlikely(invalid)) {
> + cr = 1 << CRF_SO;
> + }
> +
> + *r = ret;
> +
> + return cr;
> +}
> void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
> {
> int i;
> diff --git a/target-ppc/translate/vmx-impl.inc.c
> b/target-ppc/translate/vmx-impl.inc.c
> index e37fc11..6e54437 100644
> --- a/target-ppc/translate/vmx-impl.inc.c
> +++ b/target-ppc/translate/vmx-impl.inc.c
> @@ -991,6 +991,7 @@ GEN_BCD(bcdadd)
> GEN_BCD(bcdsub)
> GEN_BCD2(bcdcfn)
> GEN_BCD3(bcdctn)
> +GEN_BCD2(bcdcfz)
>
> static void gen_xpnd04_1(DisasContext *ctx)
> {
> @@ -1005,7 +1006,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
> gen_bcdctn(ctx);
> break;
> case 6:
> - break; /* bcdcfz. */
> + gen_bcdcfz(ctx);
> + break;
> case 7:
> gen_bcdcfn(ctx);
> break;
> @@ -1026,7 +1028,8 @@ static void gen_xpnd04_2(DisasContext *ctx)
> case 4:
> break; /* bcdctz. */
> case 6:
> - break; /* bcdcfz. */
> + gen_bcdcfz(ctx);
> + break;
> case 7:
> gen_bcdcfn(ctx);
> break;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I, Jose Ricardo Ziviani, 2016/10/28
- [Qemu-ppc] [PATCH v2 1/4] target-ppc: Implement bcdcfn. instruction, Jose Ricardo Ziviani, 2016/10/28
- [Qemu-ppc] [PATCH v2 2/4] target-ppc: Implement bcdctn. instruction, Jose Ricardo Ziviani, 2016/10/28
- [Qemu-ppc] [PATCH v2 3/4] target-ppc: Implement bcdcfz. instruction, Jose Ricardo Ziviani, 2016/10/28
- Re: [Qemu-ppc] [PATCH v2 3/4] target-ppc: Implement bcdcfz. instruction,
David Gibson <=
- [Qemu-ppc] [PATCH v2 4/4] target-ppc: Implement bcdctz. instruction, Jose Ricardo Ziviani, 2016/10/28
- Re: [Qemu-ppc] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I, David Gibson, 2016/10/30