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[Qemu-ppc] [PATCH] 4/4] target-ppc: Implement bcdctz. instruction
From: |
Jose Ricardo Ziviani |
Subject: |
[Qemu-ppc] [PATCH] 4/4] target-ppc: Implement bcdctz. instruction |
Date: |
Wed, 26 Oct 2016 11:18:58 -0200 |
bcdctz. converts from BCD to Zoned numeric format. Zoned format uses
a byte to represent a digit where the most significant nibble is 0x3
or 0xf, depending on the preferred signal.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 54 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 7 +++--
3 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index f460635..3b928b8 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -372,6 +372,7 @@ DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
DEF_HELPER_2(bcdctn, i32, avr, avr)
DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
+DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 8cbbdfc..e0a84bb 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2768,6 +2768,60 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b,
uint32_t ps)
*r = ret;
return cr;
}
+
+uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int j;
+ int cr = 0;
+ int invalid = 0;
+ uint8_t digit = 0;
+ int sgnb = bcd_get_sgn(b);
+ int zone_lead = (ps) ? 0xF0 : 0x30;
+ ppc_avr_t ret = { .u64 = { 0, 0 } };
+
+ int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0);
+ int ox_flag = (b->u64[HI_IDX] != 0);
+
+ for (i = 31, j = 16; i > 1; i -= 2, j--) {
+ digit = get_nibble(b, j);
+ ret.u8[BCD_DIG_BYTE(i)] = zone_lead + digit;
+
+ if (unlikely(digit > 9)) {
+ invalid = 1;
+ }
+ }
+
+ if (unlikely(!sgnb)) {
+ sgnb = (!get_nibble(b, 0)) ? 1 : -1;
+ }
+
+ if (ps) {
+ bcd_put_digit(&ret, (sgnb == 1) ? 0xC : 0xD, 1);
+ } else {
+ bcd_put_digit(&ret, (sgnb == 1) ? 0x3 : 0x7, 1);
+ }
+ bcd_put_digit(&ret, get_nibble(b, 1), 0);
+
+ if (!eq_flag) {
+ cr = (sgnb == 1) ? 1 << CRF_GT : 1 << CRF_LT;
+ } else {
+ cr = 1 << CRF_EQ;
+ }
+
+ if (ox_flag) {
+ cr |= 1 << CRF_SO;
+ }
+
+ if (unlikely(invalid)) {
+ cr = 1 << CRF_SO;
+ }
+
+ *r = ret;
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c
b/target-ppc/translate/vmx-impl.inc.c
index 9192f8f..62c44f0 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -918,6 +918,7 @@ GEN_BCD(bcdsub)
GEN_BCD2(bcdcfn)
GEN_BCD3(bcdctn)
GEN_BCD2(bcdcfz)
+GEN_BCD2(bcdctz)
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -927,7 +928,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
case 2:
break; /* bcdcfsq. */
case 4:
- break; /* bcdctz. */
+ gen_bcdctz(ctx);
+ break;
case 5:
gen_bcdctn(ctx);
break;
@@ -952,7 +954,8 @@ static void gen_xpnd04_2(DisasContext *ctx)
case 2:
break; /* bcdcfsq. */
case 4:
- break; /* bcdctz. */
+ gen_bcdctz(ctx);
+ break;
case 6:
gen_bcdcfz(ctx);
break;
--
2.7.4
- [Qemu-ppc] [PATCH] 3/4] target-ppc: Implement bcdcfz. instruction, (continued)
- [Qemu-ppc] [PATCH] 4/4] target-ppc: Implement bcdctz. instruction,
Jose Ricardo Ziviani <=