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Re: [Qemu-ppc] [PATCH v4 17/20] ppc/pnv: Add cut down PSI bridge model a
From: |
Cédric Le Goater |
Subject: |
Re: [Qemu-ppc] [PATCH v4 17/20] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt |
Date: |
Fri, 14 Oct 2016 10:07:53 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 |
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -318,15 +318,24 @@ static void ppc_powernv_reset(void)
>> * have a CPLD that will collect the SerIRQ and shoot them as a
>> * single level interrupt to the P8 chip. So let's setup a hook
>> * for doing just that.
>> - *
>> - * Note: The actual interrupt input isn't emulated yet, this will
>> - * come with the PSI bridge model.
>> */
>> static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
>> {
>> - /* We don't yet emulate the PSI bridge which provides the external
>> - * interrupt, so just drop interrupts on the floor
>> - */
>> + static uint32_t irqstate;
>
> Hmm.. static local with important state? That it's not clear whether
> it should be per-chip or not?
>
> I'm not averse to hacks for early bringup, but it should at least have
> a FIXME comment on it.
yes. I will see if I can make a "irq_cpld' attribute of the chip instead.
It should be cleaner.
Thanks,
C.
[Qemu-ppc] [PATCH v4 18/20] ppc/pnv: Add OCC model stub with interrupt support, Cédric Le Goater, 2016/10/03
[Qemu-ppc] [PATCH v4 19/20] ppc/pnv: Add Naples chip support for LPC interrupts, Cédric Le Goater, 2016/10/03
[Qemu-ppc] [PATCH v4 20/20] ppc/pnv: add support for POWER9 LPC Controller, Cédric Le Goater, 2016/10/03
Re: [Qemu-ppc] [Qemu-devel] [PATCH v4 00/20] ppc/pnv: booting the kernel and reaching user space, no-reply, 2016/10/03