Re: [Qemu-ppc] [PATCH v4 19/20] ppc/pnv: Add Naples chip support for LPC interrupts

[Cédric Le Goater]

On 10/14/2016 08:36 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:55AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <address@hidden>
>>
>> It adds the Naples chip which supports proper LPC interrupts via the
>> LPC controller rather than via an external CPLD.
>>
>> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
>> [clg: - updated for qemu-2.7
>>       - ported on latest PowerNV patchset (v3) ]
>> Signed-off-by: Cédric Le Goater <address@hidden>
>> ---
>>  hw/ppc/pnv.c             | 18 +++++++++++++++++-
>>  hw/ppc/pnv_lpc.c         | 47 
>> +++++++++++++++++++++++++++++++++++++++++++++--
>>  include/hw/ppc/pnv_lpc.h |  7 +++++++
>>  3 files changed, 69 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index e805e97d4d87..5b70ccf66fac 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -340,7 +340,17 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, 
>> int n, int level)
>>  
>>  static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
>>  {
>> -     /* XXX TODO */
>> +    PnvLpcController *lpc = opaque;
>> +
>> +    if (n >= ISA_NUM_IRQS) {
>> +        return;
>> +    }
> 
> How could n >= ISA_NUM_IRQS arise?  Would it have to mean a bug
> elsewhere in your code?  If so this should be an assert().

It cannot. I should remove it.

Thanks,

C.