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Re: [Qemu-ppc] [PATCH 3/4] target-ppc: implement xxbr[qdwh] instruction
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-ppc] [PATCH 3/4] target-ppc: implement xxbr[qdwh] instruction |
Date: |
Mon, 10 Oct 2016 21:13:28 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Richard Henderson <address@hidden> writes:
> On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
>> +static void gen_xxbrq(DisasContext *ctx)
>> +{
>> + TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
>> + TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
>> + TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
>> + TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
>> +
>> + if (unlikely(!ctx->vsx_enabled)) {
>> + gen_exception(ctx, POWERPC_EXCP_VSXU);
>> + return;
>> + }
>> + tcg_gen_bswap64_i64(xth, xbl);
>> + tcg_gen_bswap64_i64(xtl, xbh);
>> +}
>
> You need a temporary for the case of T==B. You don't want to overwrite XBH
> with XTH before you consume the input.
Ah.. right. Sure will change.
Regards,
Nikunj
- [Qemu-ppc] [PATCH 0/4] POWER9 TCG enablements - part6, Nikunj A Dadhania, 2016/10/07
- [Qemu-ppc] [PATCH 2/4] target-ppc: implement vnegw/d instructions, Nikunj A Dadhania, 2016/10/07
- [Qemu-ppc] [PATCH 1/4] target-ppc: implement vexts[bh]2w and vexts[bhw]2d, Nikunj A Dadhania, 2016/10/07
- [Qemu-ppc] [PATCH 3/4] target-ppc: implement xxbr[qdwh] instruction, Nikunj A Dadhania, 2016/10/07
- [Qemu-ppc] [PATCH 4/4] target-ppc: Add xscmp[eq, gt, ge, ne]dp instructions, Nikunj A Dadhania, 2016/10/07
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part6, no-reply, 2016/10/10