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[Qemu-ppc] [PULL 128/130] target-ppc: Introduce hypervisor call H_GET_TC
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 128/130] target-ppc: Introduce hypervisor call H_GET_TCE |
Date: |
Fri, 7 Mar 2014 00:34:15 +0100 |
From: Laurent Dufour <address@hidden>
This patch introduces the hypervisor call H_GET_TCE which is basically the
reverse of H_PUT_TCE, as defined in the Power Architecture Platform
Requirements (PAPR).
The hcall H_GET_TCE is required by the kdump kernel which is calling it to
retrieve the TCE set up by the panicing kernel.
Signed-off-by: Laurent Dufour <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
hw/ppc/spapr_iommu.c | 37 +++++++++++++++++++++++++++++++++++++
trace-events | 1 +
2 files changed, 38 insertions(+)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index ef45f4f..d9fe946 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -243,6 +243,42 @@ static target_ulong h_put_tce(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
return ret;
}
+static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
+ target_ulong *tce)
+{
+ if (ioba >= tcet->window_size) {
+ hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
+ TARGET_FMT_lx "\n", ioba);
+ return H_PARAMETER;
+ }
+
+ *tce = tcet->table[ioba >> SPAPR_TCE_PAGE_SHIFT];
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPREnvironment *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ target_ulong liobn = args[0];
+ target_ulong ioba = args[1];
+ target_ulong tce = 0;
+ target_ulong ret = H_PARAMETER;
+ sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
+
+ ioba &= ~(SPAPR_TCE_PAGE_SIZE - 1);
+
+ if (tcet) {
+ ret = get_tce_emu(tcet, ioba, &tce);
+ if (!ret) {
+ args[0] = tce;
+ }
+ }
+ trace_spapr_iommu_get(liobn, ioba, ret, tce);
+
+ return ret;
+}
+
int spapr_dma_dt(void *fdt, int node_off, const char *propname,
uint32_t liobn, uint64_t window, uint32_t size)
{
@@ -295,6 +331,7 @@ static void spapr_tce_table_class_init(ObjectClass *klass,
void *data)
/* hcall-tce */
spapr_register_hypercall(H_PUT_TCE, h_put_tce);
+ spapr_register_hypercall(H_GET_TCE, h_get_tce);
}
static TypeInfo spapr_tce_table_info = {
diff --git a/trace-events b/trace-events
index bd9a1cf..777f703 100644
--- a/trace-events
+++ b/trace-events
@@ -1136,6 +1136,7 @@ xics_ics_eoi(int nr) "ics_eoi: irq %#x"
# hw/ppc/spapr_iommu.c
spapr_iommu_put(uint64_t liobn, uint64_t ioba, uint64_t tce, uint64_t ret)
"liobn=%"PRIx64" ioba=0x%"PRIx64" tce=0x%"PRIx64" ret=%"PRId64
+spapr_iommu_get(uint64_t liobn, uint64_t ioba, uint64_t ret, uint64_t tce)
"liobn=%"PRIx64" ioba=0x%"PRIx64" ret=%"PRId64" tce=0x%"PRIx64
spapr_iommu_xlate(uint64_t liobn, uint64_t ioba, uint64_t tce, unsigned perm,
unsigned pgsize) "liobn=%"PRIx64" 0x%"PRIx64" -> 0x%"PRIx64" perm=%u mask=%x"
spapr_iommu_new_table(uint64_t liobn, void *tcet, void *table, int fd)
"liobn=%"PRIx64" tcet=%p table=%p fd=%d"
--
1.8.1.4
- [Qemu-ppc] [PULL 120/130] target-ppc/translate.c: Use ULL suffix for 64 bit constants, (continued)
- [Qemu-ppc] [PULL 120/130] target-ppc/translate.c: Use ULL suffix for 64 bit constants, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 106/130] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 109/130] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 108/130] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 103/130] target-ppc: Altivec 2.07: Vector Population Count Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 098/130] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 107/130] target-ppc: Altivec 2.07: Vector Merge Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 110/130] target-ppc: Altivec 2.07: Quadword Addition and Subtracation, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 126/130] target-ppc: Change the hpte store API, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 127/130] target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 128/130] target-ppc: Introduce hypervisor call H_GET_TCE,
Alexander Graf <=
- [Qemu-ppc] [PULL 122/130] target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 040/130] target-ppc: VSX Stage 4: Add xsmulsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 028/130] target-ppc: Add VSX xscmp*dp Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 035/130] target-ppc: VSX Stage 4: Refactor lxsdx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 025/130] target-ppc: Add VSX ISA2.06 xtdiv Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 044/130] target-ppc: VSX Stage 4: add xsrsqrtesp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 050/130] target-ppc: Scalar Round to Single Precision, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 045/130] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 030/130] target-ppc: Add VSX Vector Compare Instructions, Alexander Graf, 2014/03/06