Re: [Qemu-ppc] [Qemu-devel] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions

[Richard Henderson]

On 01/14/2014 06:14 AM, Tom Musta wrote:
> However, the word versions are a bit more tricky.  The VSR operand is always
> an i64.  However, the GPR operand is either an i32 (on 32-bit implementations)
> or a part of an i64.  I could not find single TCG operations to handle
> these cases.  Specifically, here is what I think doesn't work with your
> suggestions:
> 
> (1) Using tcg_gen_ext32u_tl for mfvsrwz does not compile on 32-bit PPC -- the
> ext32u_tl operation is equivalent to mov_i32 but the source operand (VSRH) is
> an i64.
> 
> (2) Using tcg_gen_ext_tl_i64 for mtvsrwa compiles but is incorrect on 64-bit 
> PPC
> -- the ext_tl_i64 translates to mov_i64.  The instruction semantic is to sign
> extend the lower 32 bits of the 64-bit source GPR.
> 
> (3) Similarly, using tcg_gen_extu_tl_i64 for mtvsrwz is incorrect for 64-bit
> PPC -- this is a mov_i64 and hence does not zero out the upper 32 bits of the
> target VSRH.

Hmm, you're right that there's not one symbol that does the job for each case.
However, there's an opcode that does the job for each case.  So perhaps we need

#ifdef TARGET_PPC64
#define ppc_gen_mfcsrwz    tcg_gen_ext32u_i64
#define ppc_gen_mtvsrwa    tcg_gen_ext32s_i64
#define ppc_gen_mtvsrwz    tcg_gen_ext32u_i64
#else
#define ppc_gen_mfcsrwz    tcg_gen_trunc_i64_i32
#define ppc_gen_mtvsrwa    tcg_gen_ext_i32_i64
#define ppc_gen_mtvsrwz    tcg_gen_extu_i32_i64
#endif

and then use those within your other macros.


r~