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Re: Emulating graviton G3

From: Peter Maydell
Subject: Re: Emulating graviton G3
Date: Fri, 3 Mar 2023 11:01:55 +0000

On Fri, 3 Mar 2023 at 07:27, Robert Henry <robhenry@microsoft.com> wrote:
> I cannot figure out how to make QEMU TCG emulate aarch64 Graviton G3.  I'm 
> working against master/head of the QEMU source.
> I come up with feature names by consulting 
> https://marcin.juszkiewicz.com.pl/download/tables/arm-socs.html which is 
> compendium of the /proc/cpuinfo info crowd sourced from linux running on real 
> systems
> I'm trying to either (a) add features to QEMU's '-cpu neoverse-n1,...' or (b) 
> take features away from '-cpu max,...'
> Unfortunately, many names of implemented or unimplemented features are not 
> known by the -cpu mechanism.  For example, from max I want to kill 
> "smeb16f32", or from neoverse-n1 I want to add in "svei8mm", but neither name 
> is known.  Indeed, the only names known by -cpu are those exposed via the qmp 
> mechanism are of the form  "sveNNN" for vector bit width NNN.
> Is there some trick I'm missing?

Broadly speaking, we do not expose most architectural-level
features via the '-cpu,+foo' option syntax. We only do that
for features where it seems "important" to give users that
level of control, or where we need to model multiple machine
types that have differently-configured CPUs of the same type in
real hardware.

So your options are:
 * use one of the pre-defined CPU types
 * use 'max' to get everything
 * write a patch to define a new CPU model type that gets
   the ID registers and feature settings right. If there are
   features that we don't emulate yet then they need to be
   implemented first

In this specific case, the Graviton G3 is a Neoverse-V1.
That CPU is on Linaro's todo-list to implement:
The only missing pieces at the moment are:
 * FEAT_LSE2 support (there are patches on list for this,
   which might or might not make it into 8.0)
 * writing the function to define the CPU type (which is

-- PMM

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