RE: What does soft-mmu mean? What happens when we set MMU registers? (aarch64)

[ckim]

I found If I turn off the 'M' bit (MMU on) of x0 before I write it to 
sctrl_el3, sctrl_el2, and sctrl_el1, it doesn't cause exception.
So it's related to MMU (not SMMU of course). And using the -d int,exec,in_asm, 
the EC(exception class) was "“Instruction Abort taken without a change in 
Exception level k”.
Below is the debug output (from -d int,exec,in_asm), exception is caused at 
"msr sctlr_el3, x0".

IN:
0x0000024c:  d53e1000  mrs      x0, sctlr_el3
0x00000250:  b27e0000  orr      x0, x0, #4
0x00000254:  b2740000  orr      x0, x0, #0x1000
0x00000258:  b2400000  orr      x0, x0, #1
0x0000025c:  926cf800  and      x0, x0, #0xfffffffffff7ffff
0x00000260:  b27d0000  orr      x0, x0, #8
0x00000264:  927ef800  and      x0, x0, #0xfffffffffffffffd
0x00000268:  d53e1002  mrs      x2, sctlr_el3    <-- just to check initial value
0x0000026c:  d53c1002  mrs      x2, sctlr_el2    <-- just to check initial value
0x00000270:  d5381002  mrs      x2, sctlr_el1    <-- just to check initial value
0x00000274:  d51e1000  msr      sctlr_el3, x0    <-- exception happens.

Trace 0: 0x7f82e73844c0 [0000000000000000/000000000000024c/0x8a100000]
Taking exception 3 [Prefetch Abort]
...from EL3 to EL3
...with ESR 0x21/0x86000010
...with FAR 0x278
...with ELR 0x278
...to EL3 PC 0x1200 PSTATE 0x3cd
Taking exception 3 [Prefetch Abort]
...from EL3 to EL3
...with ESR 0x21/0x86000010
...with FAR 0x1200
...with ELR 0x1200
...to EL3 PC 0x1200 PSTATE 0x3cd

I thought because I'm running a code for the newer architecture (v8.4) on 
cortex-a72(v8.0), there maybe be some bits that should have not turned on in x0 
register or 
Some registers or page table until this point.
I would appreciate any advice on this.

Thank you!

Chan Kim
> -----Original Message-----
> From: ckim@etri.re.kr <ckim@etri.re.kr>
> Sent: Tuesday, March 9, 2021 9:42 AM
> To: 'Peter Maydell' <peter.maydell@linaro.org>
> Cc: 'qemu-discuss' <qemu-discuss@nongnu.org>
> Subject: RE: What does soft-mmu mean? What happens when we set MMU
> registers? (aarch64)
> 
> 
> Hello, Peter Maydell,
> Thanks again for the clarifications.
> I checked I was at EL3 (read currentel), the sctlr_el3 and sctlr_el1 was
> at initialized value, but sctlr_el2 was zero. I'll look through the SMMU
> document and sctlr_el3 related contents.
> Thank you!
> Best regards,
> Chan Kim
> 
> > -----Original Message-----
> > From: Peter Maydell <peter.maydell@linaro.org>
> > Sent: Monday, March 8, 2021 10:47 PM
> > To: Chan Kim <ckim@etri.re.kr>
> > Cc: qemu-discuss <qemu-discuss@nongnu.org>
> > Subject: Re: What does soft-mmu mean? What happens when we set MMU
> > registers? (aarch64)
> >
> > On Mon, 8 Mar 2021 at 13:34, <ckim@etri.re.kr> wrote:
> > >
> > > As far as I understand, in arm architecture, access to SMMU is done
> > > by system registers,
> > >
> > > not by reading or writing to certain registers located in certain
> > addresses.
> >
> > Your understanding is incorrect. The SMMUv3 is programmed via a set of
> > memory-mapped registers (and by setting up data structures in guest
> > memory and telling the SMMU about them by writing to its registers).
> > (See the
> > SMMUv3 architecture specification, chapter 6.)
> >
> > > And I launched qemu using this command :
> > >
> > > ${QEMU_DIR}/qemu-system-aarch64 -machine
> > > type=virt,gic-version=3,secure=true,virtualization=true -cpu
> > > cortex-a72
> > >
> > > -nographic -smp 1 -m 2048 -drive
> > > if=pflash,file=pflash.img,format=raw,readonly=on
> > >
> > > I found setting sctlr_el3 caused exception (for smmu setting),
> > > trying to find what is the difference that makes this error (the
> > > baremetal code I run on qemu runs ok in rtl sim),
> >
> > SCTLR_EL3 is not related to the SMMU at all.
> >
> > The MMU and the SMMU are entirely different. The MMU is part of the
> > CPU and is used to control whether CPU memory accesses are allowed and
> > how their addresses are translated to physical addresses. The SMMU is
> > what Intel call an 'iommu', and controls whether device DMA accesses
> > are allowed and how their addresses are translated.
> >
> > > I remembered qemu I run is something called ‘soft-mmu’, so maybe I
> > shouldn’t set the mmu registers..
> >
> > "softmmu" just means "we emulate the MMU in software". It is the
> > opposite of "user-mode", where we don't emulate the MMU at all (and
> > just run one guest Linux binary).
> >
> > > In codes for SoCs with real mmu, how does the codes work when it
> > > sets
> > MMU related registers?
> >
> > This works because QEMU emulates the MMU.
> >
> > If you're getting an exception when you try to write to SCTLR_EL3, you
> > should check whether (for instance) you're actually executing at EL3.
> > QEMU's debug logging options might help in working out why an
> > exception was taken.
> >
> > thanks
> > -- PMM