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[PATCH v2 05/21] Hexagon (target/hexagon) Add overrides for clr[tf]new
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From: |
Taylor Simpson |
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Subject: |
[PATCH v2 05/21] Hexagon (target/hexagon) Add overrides for clr[tf]new |
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Date: |
Thu, 27 Apr 2023 15:59:56 -0700 |
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 16 ++++++++++++++++
target/hexagon/macros.h | 4 ----
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 7c5cb93297..f3e9c280b0 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1097,6 +1097,22 @@
gen_jump(ctx, riV); \
} while (0)
+/* if (p0.new) r0 = #0 */
+#define fGEN_TCG_SA1_clrtnew(SHORTCODE) \
+ do { \
+ tcg_gen_movcond_tl(TCG_COND_EQ, RdV, \
+ hex_new_pred_value[0], tcg_constant_tl(0), \
+ RdV, tcg_constant_tl(0)); \
+ } while (0)
+
+/* if (!p0.new) r0 = #0 */
+#define fGEN_TCG_SA1_clrfnew(SHORTCODE) \
+ do { \
+ tcg_gen_movcond_tl(TCG_COND_NE, RdV, \
+ hex_new_pred_value[0], tcg_constant_tl(0), \
+ RdV, tcg_constant_tl(0)); \
+ } while (0)
+
#define fGEN_TCG_J2_pause(SHORTCODE) \
do { \
uiV = uiV; \
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 3e162de3a7..2cb0647ce2 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -227,12 +227,8 @@ static inline void gen_cancel(uint32_t slot)
#ifdef QEMU_GENERATE
#define fLSBNEW(PVAL) tcg_gen_andi_tl(LSB, (PVAL), 1)
-#define fLSBNEW0 tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
-#define fLSBNEW1 tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
#else
#define fLSBNEW(PVAL) ((PVAL) & 1)
-#define fLSBNEW0 (env->new_pred_value[0] & 1)
-#define fLSBNEW1 (env->new_pred_value[1] & 1)
#endif
#ifdef QEMU_GENERATE
--
2.25.1
- [PATCH v2 00/21] Hexagon (target/hexagon) short-circuit and move to DisasContext, Taylor Simpson, 2023/04/27
- [PATCH v2 06/21] Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch], Taylor Simpson, 2023/04/27
- [PATCH v2 02/21] Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write, Taylor Simpson, 2023/04/27
- [PATCH v2 05/21] Hexagon (target/hexagon) Add overrides for clr[tf]new,
Taylor Simpson <=
- [PATCH v2 04/21] Hexagon (target/hexagon) Add overrides for allocframe/deallocframe, Taylor Simpson, 2023/04/27
- [PATCH v2 12/21] Hexagon (target/hexagon) Short-circuit packet predicate writes, Taylor Simpson, 2023/04/27
- [PATCH v2 03/21] Hexagon (target/hexagon) Add overrides for loop setup instructions, Taylor Simpson, 2023/04/27
- [PATCH v2 07/21] Hexagon (target/hexagon) Eliminate uses of log_pred_write function, Taylor Simpson, 2023/04/27
- [PATCH v2 15/21] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns, Taylor Simpson, 2023/04/27
- [PATCH v2 19/21] Hexagon (target/hexagon) Move pred_written to DisasContext, Taylor Simpson, 2023/04/27
- [PATCH v2 14/21] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets, Taylor Simpson, 2023/04/27
- [PATCH v2 09/21] Hexagon (target/hexagon) Don't overlap dest writes with source reads, Taylor Simpson, 2023/04/27