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[PATCH v3 27/47] igb: Clear EICR bits for delayed MSI-X interrupts
From: |
Akihiko Odaki |
Subject: |
[PATCH v3 27/47] igb: Clear EICR bits for delayed MSI-X interrupts |
Date: |
Sun, 23 Apr 2023 13:18:13 +0900 |
Section 7.3.4.1 says:
> When auto-clear is enabled for an interrupt cause, the EICR bit is
> set when a cause event mapped to this vector occurs. When the EITR
> Counter reaches zero, the MSI-X message is sent on PCIe. Then the
> EICR bit is cleared and enabled to be set by a new cause event
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
hw/net/igb_core.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 3c1ef11afd..ef29e68096 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -97,23 +97,31 @@ igb_lower_legacy_irq(IGBCore *core)
pci_set_irq(core->owner, 0);
}
-static void igb_msix_notify(IGBCore *core, unsigned int vector)
+static void igb_msix_notify(IGBCore *core, unsigned int cause)
{
PCIDevice *dev = core->owner;
uint16_t vfn;
+ uint32_t effective_eiac;
+ unsigned int vector;
- vfn = 8 - (vector + 2) / IGBVF_MSIX_VEC_NUM;
+ vfn = 8 - (cause + 2) / IGBVF_MSIX_VEC_NUM;
if (vfn < pcie_sriov_num_vfs(core->owner)) {
dev = pcie_sriov_get_vf_at_index(core->owner, vfn);
assert(dev);
- vector = (vector + 2) % IGBVF_MSIX_VEC_NUM;
- } else if (vector >= IGB_MSIX_VEC_NUM) {
+ vector = (cause + 2) % IGBVF_MSIX_VEC_NUM;
+ } else if (cause >= IGB_MSIX_VEC_NUM) {
qemu_log_mask(LOG_GUEST_ERROR,
"igb: Tried to use vector unavailable for PF");
return;
+ } else {
+ vector = cause;
}
msix_notify(dev, vector);
+
+ trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]);
+ effective_eiac = core->mac[EIAC] & BIT(cause);
+ core->mac[EICR] &= ~effective_eiac;
}
static inline void
@@ -1834,7 +1842,6 @@ igb_eitr_should_postpone(IGBCore *core, int idx)
static void igb_send_msix(IGBCore *core)
{
uint32_t causes = core->mac[EICR] & core->mac[EIMS];
- uint32_t effective_eiac;
int vector;
for (vector = 0; vector < IGB_INTR_NUM; ++vector) {
@@ -1842,10 +1849,6 @@ static void igb_send_msix(IGBCore *core)
trace_e1000e_irq_msix_notify_vec(vector);
igb_msix_notify(core, vector);
-
- trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]);
- effective_eiac = core->mac[EIAC] & BIT(vector);
- core->mac[EICR] &= ~effective_eiac;
}
}
}
--
2.40.0
- [PATCH v3 17/47] e1000x: Rename TcpIpv6 into TcpIpv6Ex, (continued)
- [PATCH v3 17/47] e1000x: Rename TcpIpv6 into TcpIpv6Ex, Akihiko Odaki, 2023/04/23
- [PATCH v3 19/47] igb: Always log status after building rx metadata, Akihiko Odaki, 2023/04/23
- [PATCH v3 21/47] igb: Read DCMD.VLE of the first Tx descriptor, Akihiko Odaki, 2023/04/23
- [PATCH v3 23/47] vmxnet3: Reset packet state after emptying Tx queue, Akihiko Odaki, 2023/04/23
- [PATCH v3 20/47] igb: Remove goto, Akihiko Odaki, 2023/04/23
- [PATCH v3 22/47] e1000e: Reset packet state after emptying Tx queue, Akihiko Odaki, 2023/04/23
- [PATCH v3 18/47] e1000e: Always log status after building rx metadata, Akihiko Odaki, 2023/04/23
- [PATCH v3 24/47] igb: Add more definitions for Tx descriptor, Akihiko Odaki, 2023/04/23
- [PATCH v3 25/47] igb: Share common VF constants, Akihiko Odaki, 2023/04/23
- [PATCH v3 26/47] igb: Fix igb_mac_reg_init coding style alignment, Akihiko Odaki, 2023/04/23
- [PATCH v3 27/47] igb: Clear EICR bits for delayed MSI-X interrupts,
Akihiko Odaki <=
- [PATCH v3 29/47] igb: Rename a variable in igb_receive_internal(), Akihiko Odaki, 2023/04/23
- [PATCH v3 30/47] net/eth: Use void pointers, Akihiko Odaki, 2023/04/23
- [PATCH v3 28/47] e1000e: Rename a variable in e1000e_receive_internal(), Akihiko Odaki, 2023/04/23
- [PATCH v3 31/47] net/eth: Always add VLAN tag, Akihiko Odaki, 2023/04/23
- [PATCH v3 33/47] tests/qtest/libqos/igb: Set GPIE.Multiple_MSIX, Akihiko Odaki, 2023/04/23
- [PATCH v3 35/47] igb: Use UDP for RSS hash, Akihiko Odaki, 2023/04/23
- [PATCH v3 36/47] igb: Implement Rx SCTP CSO, Akihiko Odaki, 2023/04/23
- [PATCH v3 34/47] igb: Implement MSI-X single vector mode, Akihiko Odaki, 2023/04/23