[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 10/11] Hexagon (target/hexagon) Add overrides for cache/sync/barri
From: |
Taylor Simpson |
Subject: |
[PULL 10/11] Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions |
Date: |
Wed, 19 Apr 2023 20:26:33 -0700 |
Most of these are not modelled in QEMU, so save the overhead of
calling a helper.
The only exception is dczeroa. It assigns to hex_dczero_addr, which
is handled during packet commit.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230410202402.2856852-1-tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 24 ++++++++++++++++++++++++
target/hexagon/macros.h | 18 ++++--------------
2 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index b189f725d7..329e7a1024 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -487,6 +487,19 @@
#define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \
fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN))
+/* dczeroa clears the 32 byte cache line at the address given */
+#define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE
+
+/* In linux-user mode, these are not modelled, suppress compiler warning */
+#define fGEN_TCG_Y2_dcinva(SHORTCODE) \
+ do { RsV = RsV; } while (0)
+#define fGEN_TCG_Y2_dccleaninva(SHORTCODE) \
+ do { RsV = RsV; } while (0)
+#define fGEN_TCG_Y2_dccleana(SHORTCODE) \
+ do { RsV = RsV; } while (0)
+#define fGEN_TCG_Y2_icinva(SHORTCODE) \
+ do { RsV = RsV; } while (0)
+
/*
* dealloc_return
* Assembler mapped to
@@ -1211,6 +1224,17 @@
do { \
RsV = RsV; \
} while (0)
+#define fGEN_TCG_Y2_isync(SHORTCODE) \
+ do { } while (0)
+#define fGEN_TCG_Y2_barrier(SHORTCODE) \
+ do { } while (0)
+#define fGEN_TCG_Y2_syncht(SHORTCODE) \
+ do { } while (0)
+#define fGEN_TCG_Y2_dcfetchbo(SHORTCODE) \
+ do { \
+ RsV = RsV; \
+ uiV = uiV; \
+ } while (0)
#define fGEN_TCG_J2_trap0(SHORTCODE) \
do { \
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 9ddfc91b1d..3e162de3a7 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -659,20 +659,10 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
int shift)
fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
reg_field_info[FIELD].width, \
reg_field_info[FIELD].offset)
-#define fBARRIER()
-#define fSYNCH()
-#define fISYNC()
-#define fDCFETCH(REG) \
- do { (void)REG; } while (0) /* Nothing to do in qemu */
-#define fICINVA(REG) \
- do { (void)REG; } while (0) /* Nothing to do in qemu */
-#define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
-#define fDCCLEANA(REG) \
- do { (void)REG; } while (0) /* Nothing to do in qemu */
-#define fDCCLEANINVA(REG) \
- do { (void)REG; } while (0) /* Nothing to do in qemu */
-
-#define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
+
+#ifdef QEMU_GENERATE
+#define fDCZEROA(REG) tcg_gen_mov_tl(hex_dczero_addr, (REG))
+#endif
#define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
STRBITNUM) /* Nothing */
--
2.25.1
- [PULL 00/11] Hexagon queue, Taylor Simpson, 2023/04/19
- [PULL 05/11] Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_stores, Taylor Simpson, 2023/04/19
- [PULL 07/11] Hexagon (target/hexagon) Updates to USR should use get_result_gpr, Taylor Simpson, 2023/04/19
- [PULL 01/11] Hexagon (translate.c): avoid redundant PC updates on COF, Taylor Simpson, 2023/04/19
- [PULL 11/11] Hexagon (target/hexagon) Additional instructions handled by idef-parser, Taylor Simpson, 2023/04/19
- [PULL 04/11] Hexagon (target/hexagon) Remove redundant/unused macros, Taylor Simpson, 2023/04/19
- [PULL 06/11] Hexagon (target/hexagon) Add overrides for count trailing zeros/ones, Taylor Simpson, 2023/04/19
- [PULL 09/11] Hexagon (target/hexagon) Remove unused slot variable in helpers, Taylor Simpson, 2023/04/19
- [PULL 08/11] Hexagon (tests/tcg/hexagon) Move HVX test infra to header file, Taylor Simpson, 2023/04/19
- [PULL 02/11] Use f-strings in python scripts, Taylor Simpson, 2023/04/19
- [PULL 10/11] Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions,
Taylor Simpson <=
- [PULL 03/11] Use black code style for python scripts, Taylor Simpson, 2023/04/19
- Re: [PULL 00/11] Hexagon queue, Richard Henderson, 2023/04/21