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[PULL 07/11] Hexagon (target/hexagon) Updates to USR should use get_resu
From: |
Taylor Simpson |
Subject: |
[PULL 07/11] Hexagon (target/hexagon) Updates to USR should use get_result_gpr |
Date: |
Wed, 19 Apr 2023 20:26:30 -0700 |
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230405164211.30015-3-tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 4 +-
target/hexagon/genptr.h | 10 ++---
target/hexagon/macros.h | 8 ----
target/hexagon/genptr.c | 49 ++++++++++-----------
target/hexagon/idef-parser/parser-helpers.c | 5 ++-
target/hexagon/idef-parser/idef-parser.y | 2 +-
6 files changed, 34 insertions(+), 44 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 45f92adf6c..b189f725d7 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1039,11 +1039,11 @@
/* r0 = asr(r1, r2):sat */
#define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \
- gen_asr_r_r_sat(RdV, RsV, RtV)
+ gen_asr_r_r_sat(ctx, RdV, RsV, RtV)
/* r0 = asl(r1, r2):sat */
#define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \
- gen_asl_r_r_sat(RdV, RsV, RtV)
+ gen_asl_r_r_sat(ctx, RdV, RsV, RtV)
#define fGEN_TCG_SL2_jumpr31(SHORTCODE) \
gen_jumpr(ctx, hex_gpr[HEX_REG_LR])
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index 591b059698..76e497aa48 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -37,9 +37,9 @@ TCGv gen_read_reg(TCGv result, int num);
TCGv gen_read_preg(TCGv pred, uint8_t num);
void gen_log_reg_write(int rnum, TCGv val);
void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
-void gen_set_usr_field(int field, TCGv val);
-void gen_set_usr_fieldi(int field, int x);
-void gen_set_usr_field_if(int field, TCGv val);
+void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
+void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
+void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val);
void gen_sat_i32(TCGv dest, TCGv source, int width);
void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
void gen_satu_i32(TCGv dest, TCGv source, int width);
@@ -48,7 +48,7 @@ void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
-void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
+void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
TCGv gen_8bitsof(TCGv result, TCGv value);
void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index f5f31b6930..21b5b5a06c 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -38,14 +38,6 @@
#define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int)
#define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv)
#define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64)
-
-#define SET_USR_FIELD_FUNC(X) \
- __builtin_choose_expr(TYPE_INT(X), \
- gen_set_usr_fieldi, \
- __builtin_choose_expr(TYPE_TCGV(X), \
- gen_set_usr_field, (void)0))
-#define SET_USR_FIELD(FIELD, VAL) \
- SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
#else
#define GET_USR_FIELD(FIELD) \
fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index bb274d4a71..502c85ae35 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -486,30 +486,27 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx, int
pc_off,
}
}
-void gen_set_usr_field(int field, TCGv val)
+void gen_set_usr_field(DisasContext *ctx, int field, TCGv val)
{
- tcg_gen_deposit_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR],
- val,
+ TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
+ tcg_gen_deposit_tl(usr, usr, val,
reg_field_info[field].offset,
reg_field_info[field].width);
}
-void gen_set_usr_fieldi(int field, int x)
+void gen_set_usr_fieldi(DisasContext *ctx, int field, int x)
{
if (reg_field_info[field].width == 1) {
+ TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
target_ulong bit = 1 << reg_field_info[field].offset;
if ((x & 1) == 1) {
- tcg_gen_ori_tl(hex_new_value[HEX_REG_USR],
- hex_new_value[HEX_REG_USR],
- bit);
+ tcg_gen_ori_tl(usr, usr, bit);
} else {
- tcg_gen_andi_tl(hex_new_value[HEX_REG_USR],
- hex_new_value[HEX_REG_USR],
- ~bit);
+ tcg_gen_andi_tl(usr, usr, ~bit);
}
} else {
TCGv val = tcg_constant_tl(x);
- gen_set_usr_field(field, val);
+ gen_set_usr_field(ctx, field, val);
}
}
@@ -754,7 +751,7 @@ static void gen_endloop0(DisasContext *ctx)
tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
{
tcg_gen_subi_tl(lpcfg, lpcfg, 1);
- SET_USR_FIELD(USR_LPCFG, lpcfg);
+ gen_set_usr_field(ctx, USR_LPCFG, lpcfg);
}
gen_set_label(label2);
@@ -829,7 +826,7 @@ static void gen_endloop01(DisasContext *ctx)
tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
{
tcg_gen_subi_tl(lpcfg, lpcfg, 1);
- SET_USR_FIELD(USR_LPCFG, lpcfg);
+ gen_set_usr_field(ctx, USR_LPCFG, lpcfg);
}
gen_set_label(label2);
@@ -878,8 +875,9 @@ static void gen_cmpi_jumpnv(DisasContext *ctx,
}
/* Shift left with saturation */
-static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
+static void gen_shl_sat(DisasContext *ctx, TCGv dst, TCGv src, TCGv shift_amt)
{
+ TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
TCGv sh32 = tcg_temp_new();
TCGv dst_sar = tcg_temp_new();
TCGv ovf = tcg_temp_new();
@@ -911,7 +909,7 @@ static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
tcg_gen_setcond_tl(TCG_COND_NE, ovf, dst_sar, src);
tcg_gen_shli_tl(ovf, ovf, reg_field_info[USR_OVF].offset);
- tcg_gen_or_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR], ovf);
+ tcg_gen_or_tl(usr, usr, ovf);
tcg_gen_movcond_tl(TCG_COND_EQ, dst, dst_sar, src, dst, satval);
}
@@ -928,7 +926,7 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
}
/* Bidirectional shift right with saturation */
-static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
+static void gen_asr_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV)
{
TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
@@ -939,7 +937,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
/* Negative shift amount => shift left */
tcg_gen_neg_tl(shift_amt, shift_amt);
- gen_shl_sat(RdV, RsV, shift_amt);
+ gen_shl_sat(ctx, RdV, RsV, shift_amt);
tcg_gen_br(done);
gen_set_label(positive);
@@ -950,7 +948,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
}
/* Bidirectional shift left with saturation */
-static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
+static void gen_asl_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV)
{
TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
@@ -966,7 +964,7 @@ static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
gen_set_label(positive);
/* Positive shift amount => shift left */
- gen_shl_sat(RdV, RsV, shift_amt);
+ gen_shl_sat(ctx, RdV, RsV, shift_amt);
gen_set_label(done);
}
@@ -1109,20 +1107,19 @@ void probe_noshuf_load(TCGv va, int s, int mi)
* Note: Since this function might branch, `val` is
* required to be a `tcg_temp_local`.
*/
-void gen_set_usr_field_if(int field, TCGv val)
+void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val)
{
/* Sets the USR field if `val` is non-zero */
if (reg_field_info[field].width == 1) {
+ TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
TCGv tmp = tcg_temp_new();
tcg_gen_extract_tl(tmp, val, 0, reg_field_info[field].width);
tcg_gen_shli_tl(tmp, tmp, reg_field_info[field].offset);
- tcg_gen_or_tl(hex_new_value[HEX_REG_USR],
- hex_new_value[HEX_REG_USR],
- tmp);
+ tcg_gen_or_tl(usr, usr, tmp);
} else {
TCGLabel *skip_label = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, val, 0, skip_label);
- gen_set_usr_field(field, val);
+ gen_set_usr_field(ctx, field, val);
gen_set_label(skip_label);
}
}
@@ -1190,7 +1187,7 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64
source, int width)
}
/* Implements the fADDSAT64 macro in TCG */
-void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
+void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 sum = tcg_temp_new_i64();
TCGv_i64 xor = tcg_temp_new_i64();
@@ -1227,7 +1224,7 @@ void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
gen_set_label(ovfl_label);
tcg_gen_and_i64(cond3, sum, mask);
tcg_gen_movcond_i64(TCG_COND_NE, ret, cond3, zero, max_pos, max_neg);
- SET_USR_FIELD(USR_OVF, 1);
+ gen_set_usr_fieldi(ctx, USR_OVF, 1);
gen_set_label(ret_label);
}
diff --git a/target/hexagon/idef-parser/parser-helpers.c
b/target/hexagon/idef-parser/parser-helpers.c
index 18cde6a1be..86511efb62 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1640,7 +1640,8 @@ void gen_addsat64(Context *c,
{
HexValue op1_m = rvalue_materialize(c, locp, op1);
HexValue op2_m = rvalue_materialize(c, locp, op2);
- OUT(c, locp, "gen_add_sat_i64(", dst, ", ", &op1_m, ", ", &op2_m, ");\n");
+ OUT(c, locp, "gen_add_sat_i64(ctx, ", dst, ", ", &op1_m, ", ",
+ &op2_m, ");\n");
}
void gen_inst(Context *c, GString *iname)
@@ -1971,7 +1972,7 @@ HexValue gen_rvalue_sat(Context *c, YYLTYPE *locp, HexSat
*sat,
OUT(c, locp, "gen_sat", unsigned_str, "_", bit_suffix, "_ovfl(");
OUT(c, locp, &ovfl, ", ", &res, ", ", value, ", ", &width->imm.value,
");\n");
- OUT(c, locp, "gen_set_usr_field_if(USR_OVF,", &ovfl, ");\n");
+ OUT(c, locp, "gen_set_usr_field_if(ctx, USR_OVF,", &ovfl, ");\n");
return res;
}
diff --git a/target/hexagon/idef-parser/idef-parser.y
b/target/hexagon/idef-parser/idef-parser.y
index 7d05773b67..5444fd4749 100644
--- a/target/hexagon/idef-parser/idef-parser.y
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -362,7 +362,7 @@ assign_statement : lvalue '=' rvalue
"Assignment side-effect not modeled!");
$3 = gen_rvalue_truncate(c, &@1, &$3);
$3 = rvalue_materialize(c, &@1, &$3);
- OUT(c, &@1, "SET_USR_FIELD(USR_LPCFG, ", &$3, ");\n");
+ OUT(c, &@1, "gen_set_usr_field(ctx, USR_LPCFG, ", &$3,
");\n");
}
| DEPOSIT '(' rvalue ',' rvalue ',' rvalue ')'
{
--
2.25.1
- [PULL 00/11] Hexagon queue, Taylor Simpson, 2023/04/19
- [PULL 05/11] Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_stores, Taylor Simpson, 2023/04/19
- [PULL 07/11] Hexagon (target/hexagon) Updates to USR should use get_result_gpr,
Taylor Simpson <=
- [PULL 01/11] Hexagon (translate.c): avoid redundant PC updates on COF, Taylor Simpson, 2023/04/19
- [PULL 11/11] Hexagon (target/hexagon) Additional instructions handled by idef-parser, Taylor Simpson, 2023/04/19
- [PULL 04/11] Hexagon (target/hexagon) Remove redundant/unused macros, Taylor Simpson, 2023/04/19
- [PULL 06/11] Hexagon (target/hexagon) Add overrides for count trailing zeros/ones, Taylor Simpson, 2023/04/19
- [PULL 09/11] Hexagon (target/hexagon) Remove unused slot variable in helpers, Taylor Simpson, 2023/04/19
- [PULL 08/11] Hexagon (tests/tcg/hexagon) Move HVX test infra to header file, Taylor Simpson, 2023/04/19
- [PULL 02/11] Use f-strings in python scripts, Taylor Simpson, 2023/04/19
- [PULL 10/11] Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions, Taylor Simpson, 2023/04/19
- [PULL 03/11] Use black code style for python scripts, Taylor Simpson, 2023/04/19
- Re: [PULL 00/11] Hexagon queue, Richard Henderson, 2023/04/21