[PATCH v2 8/8] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to update rule nums only once for each pmpcfg_csr_write. Then we can also move tlb_flush and tb_flush into pmp_update_rule_nums().

[Weiwei Li]

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/pmp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 67347c5887..1cce3f0ce4 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -122,7 +122,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t 
pmp_index, uint8_t val)
             qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
         } else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
             env->pmp_state.pmp[pmp_index].cfg_reg = val;
-            pmp_update_rule(env, pmp_index);
+            pmp_update_rule_addr(env, pmp_index);
             return true;
         }
     } else {
@@ -208,6 +208,9 @@ void pmp_update_rule_nums(CPURISCVState *env)
             env->pmp_state.num_rules++;
         }
     }
+
+    tlb_flush(env_cpu(env));
+    tb_flush(env_cpu(env));
 }
 
 /*
@@ -487,8 +490,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t 
reg_index,
 
     /* If PMP permission of any addr has been changed, flush TLB pages. */
     if (modified) {
-        tlb_flush(env_cpu(env));
-        tb_flush(env_cpu(env));
+        pmp_update_rule_nums(env);
     }
 }
 
@@ -541,8 +543,6 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t 
addr_index,
             if (env->pmp_state.pmp[addr_index].addr_reg != val) {
                 env->pmp_state.pmp[addr_index].addr_reg = val;
                 pmp_update_rule(env, addr_index);
-                tlb_flush(env_cpu(env));
-                tb_flush(env_cpu(env));
             }
         } else {
             qemu_log_mask(LOG_GUEST_ERROR,
-- 
2.25.1