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[PATCH v2 6/8] accel/tcg: Uncache the host address for instruction fetch
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From: |
Weiwei Li |
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Subject: |
[PATCH v2 6/8] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 |
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Date: |
Tue, 18 Apr 2023 22:06:30 +0800 |
When PMP entry overlap part of the page, we'll set the tlb_size to 1, which
will make the address in tlb entry set with TLB_INVALID_MASK, and the next
access will again go through tlb_fill.However, this way will not work in
tb_gen_code() => get_page_addr_code_hostp(): the TLB host address will be
cached, and the following instructions can use this host address directly
which may lead to the bypass of PMP related check.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
accel/tcg/cputlb.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index e984a98dc4..efa0cb67c9 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1696,6 +1696,11 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState
*env, target_ulong addr,
if (p == NULL) {
return -1;
}
+
+ if (full->lg_page_size < TARGET_PAGE_BITS) {
+ return -1;
+ }
+
if (hostp) {
*hostp = p;
}
--
2.25.1
- [PATCH v2 0/8] target/riscv: Fix PMP related problem, Weiwei Li, 2023/04/18
- [PATCH v2 1/8] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/04/18
- [PATCH v2 4/8] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/04/18
- [PATCH v2 6/8] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1,
Weiwei Li <=
- [PATCH v2 8/8] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to update rule nums only once for each pmpcfg_csr_write. Then we can also move tlb_flush and tb_flush into pmp_update_rule_nums()., Weiwei Li, 2023/04/18
- [PATCH v2 3/8] target/riscv: flush tlb when pmpaddr is updated, Weiwei Li, 2023/04/18
- [PATCH v2 7/8] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/04/18
- [PATCH v2 5/8] target/riscv: flush tb when PMP entry changes, Weiwei Li, 2023/04/18
- [PATCH v2 2/8] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/04/18