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[PATCH 24/40] igb: Fix igb_mac_reg_init alignment
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From: |
Akihiko Odaki |
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Subject: |
[PATCH 24/40] igb: Fix igb_mac_reg_init alignment |
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Date: |
Fri, 14 Apr 2023 20:37:21 +0900 |
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
hw/net/igb_core.c | 96 +++++++++++++++++++++++------------------------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 350462c40c..429b0ebc03 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -4027,54 +4027,54 @@ static const uint32_t igb_mac_reg_init[] = {
[VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC,
[RPLOLR] = E1000_RPLOLR_STRCRC,
[RLPML] = 0x2600,
- [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
};
static void igb_reset(IGBCore *core, bool sw)
--
2.40.0
- RE: [PATCH 18/40] igb: Remove goto, (continued)
- [PATCH 20/40] e1000e: Reset packet state after emptying Tx queue, Akihiko Odaki, 2023/04/14
- [PATCH 19/40] igb: Read DCMD.VLE of the first Tx descriptor, Akihiko Odaki, 2023/04/14
- [PATCH 22/40] igb: Add more definitions for Tx descriptor, Akihiko Odaki, 2023/04/14
- [PATCH 23/40] igb: Share common VF constants, Akihiko Odaki, 2023/04/14
- [PATCH 21/40] vmxnet3: Reset packet state after emptying Tx queue, Akihiko Odaki, 2023/04/14
- [PATCH 24/40] igb: Fix igb_mac_reg_init alignment,
Akihiko Odaki <=
- [PATCH 25/40] net/eth: Use void pointers, Akihiko Odaki, 2023/04/14
- [PATCH 26/40] net/eth: Always add VLAN tag, Akihiko Odaki, 2023/04/14
- [PATCH 28/40] tests/qtest/libqos/igb: Set GPIE.Multiple_MSIX, Akihiko Odaki, 2023/04/14
- [PATCH 27/40] hw/net/net_rx_pkt: Enforce alignment for eth_header, Akihiko Odaki, 2023/04/14
- [PATCH 29/40] igb: Implement MSI-X single vector mode, Akihiko Odaki, 2023/04/14
- [PATCH 30/40] igb: Implement igb-specific oversize check, Akihiko Odaki, 2023/04/14