Re: [PATCH v2 50/54] tcg/ppc: Adjust constraints on qemu_ld/st

[Daniel Henrique Barboza]

On 4/10/23 22:05, Richard Henderson wrote:
> The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally
> available registers.  Now that we handle overlap betwen inputs and
> helper arguments, we can allow any allocatable reg.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>

>   tcg/ppc/tcg-target-con-set.h | 11 ++++-------
>   tcg/ppc/tcg-target-con-str.h |  2 --
>   tcg/ppc/tcg-target.c.inc     | 32 ++++++++++----------------------
>   3 files changed, 14 insertions(+), 31 deletions(-)
>
> diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
> index a1a345883d..f206b29205 100644
> --- a/tcg/ppc/tcg-target-con-set.h
> +++ b/tcg/ppc/tcg-target-con-set.h
> @@ -12,18 +12,15 @@
>   C_O0_I1(r)
>   C_O0_I2(r, r)
>   C_O0_I2(r, ri)
> -C_O0_I2(S, S)
>   C_O0_I2(v, r)
> -C_O0_I3(S, S, S)
> +C_O0_I3(r, r, r)
>   C_O0_I4(r, r, ri, ri)
> -C_O0_I4(S, S, S, S)
> -C_O1_I1(r, L)
> +C_O0_I4(r, r, r, r)
>   C_O1_I1(r, r)
>   C_O1_I1(v, r)
>   C_O1_I1(v, v)
>   C_O1_I1(v, vr)
>   C_O1_I2(r, 0, rZ)
> -C_O1_I2(r, L, L)
>   C_O1_I2(r, rI, ri)
>   C_O1_I2(r, rI, rT)
>   C_O1_I2(r, r, r)
> @@ -36,7 +33,7 @@ C_O1_I2(v, v, v)
>   C_O1_I3(v, v, v, v)
>   C_O1_I4(r, r, ri, rZ, rZ)
>   C_O1_I4(r, r, r, ri, ri)
> -C_O2_I1(L, L, L)
> -C_O2_I2(L, L, L, L)
> +C_O2_I1(r, r, r)
> +C_O2_I2(r, r, r, r)
>   C_O2_I4(r, r, rI, rZM, r, r)
>   C_O2_I4(r, r, r, r, rI, rZM)
> diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
> index 298ca20d5b..f3bf030bc3 100644
> --- a/tcg/ppc/tcg-target-con-str.h
> +++ b/tcg/ppc/tcg-target-con-str.h
> @@ -14,8 +14,6 @@ REGS('A', 1u << TCG_REG_R3)
>   REGS('B', 1u << TCG_REG_R4)
>   REGS('C', 1u << TCG_REG_R5)
>   REGS('D', 1u << TCG_REG_R6)
> -REGS('L', ALL_QLOAD_REGS)
> -REGS('S', ALL_QSTORE_REGS)
>   
>   /*
>    * Define constraint letters for constants:
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index 613cd73583..e94f3131a3 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -93,18 +93,6 @@
>   #define ALL_GENERAL_REGS  0xffffffffu
>   #define ALL_VECTOR_REGS   0xffffffff00000000ull
>   
> -#ifdef CONFIG_SOFTMMU
> -#define ALL_QLOAD_REGS \
> -    (ALL_GENERAL_REGS & \
> -     ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
> -#define ALL_QSTORE_REGS \
> -    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
> -                          (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
> -#else
> -#define ALL_QLOAD_REGS  (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
> -#define ALL_QSTORE_REGS ALL_QLOAD_REGS
> -#endif
> -
>   TCGPowerISA have_isa;
>   static bool have_isel;
>   bool have_altivec;
> @@ -3791,23 +3779,23 @@ static TCGConstraintSetIndex 
> tcg_target_op_def(TCGOpcode op)
>   
>       case INDEX_op_qemu_ld_i32:
>           return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
> -                ? C_O1_I1(r, L)
> -                : C_O1_I2(r, L, L));
> +                ? C_O1_I1(r, r)
> +                : C_O1_I2(r, r, r));
>   
>       case INDEX_op_qemu_st_i32:
>           return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
> -                ? C_O0_I2(S, S)
> -                : C_O0_I3(S, S, S));
> +                ? C_O0_I2(r, r)
> +                : C_O0_I3(r, r, r));
>   
>       case INDEX_op_qemu_ld_i64:
> -        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
> -                : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
> -                : C_O2_I2(L, L, L, L));
> +        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
> +                : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, r)
> +                : C_O2_I2(r, r, r, r));
>   
>       case INDEX_op_qemu_st_i64:
> -        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
> -                : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
> -                : C_O0_I4(S, S, S, S));
> +        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r)
> +                : TARGET_LONG_BITS == 32 ? C_O0_I3(r, r, r)
> +                : C_O0_I4(r, r, r, r));
>   
>       case INDEX_op_add_vec:
>       case INDEX_op_sub_vec: