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[PATCH v2 52/54] tcg/riscv: Simplify constraints on qemu_ld/st
From: |
Richard Henderson |
Subject: |
[PATCH v2 52/54] tcg/riscv: Simplify constraints on qemu_ld/st |
Date: |
Mon, 10 Apr 2023 18:05:10 -0700 |
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers. Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-con-set.h | 2 --
tcg/riscv/tcg-target-con-str.h | 1 -
tcg/riscv/tcg-target.c.inc | 16 +++-------------
3 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
index c11710d117..1a8b8e9f2b 100644
--- a/tcg/riscv/tcg-target-con-set.h
+++ b/tcg/riscv/tcg-target-con-set.h
@@ -10,11 +10,9 @@
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
-C_O0_I2(LZ, L)
C_O0_I2(rZ, r)
C_O0_I2(rZ, rZ)
C_O0_I4(rZ, rZ, rZ, rZ)
-C_O1_I1(r, L)
C_O1_I1(r, r)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
index 8d8afaee53..6f1cfb976c 100644
--- a/tcg/riscv/tcg-target-con-str.h
+++ b/tcg/riscv/tcg-target-con-str.h
@@ -9,7 +9,6 @@
* REGS(letter, register_mask)
*/
REGS('r', ALL_GENERAL_REGS)
-REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
/*
* Define constraint letters for constants:
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 425ea8902e..35f04ddda9 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -125,17 +125,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind
kind, int slot)
#define TCG_CT_CONST_N12 0x400
#define TCG_CT_CONST_M12 0x800
-#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
-/*
- * For softmmu, we need to avoid conflicts with the first 5
- * argument registers to call the helper. Some of these are
- * also used for the tlb lookup.
- */
-#ifdef CONFIG_SOFTMMU
-#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5)
-#else
-#define SOFTMMU_RESERVE_REGS 0
-#endif
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
#define sextreg sextract64
@@ -1653,10 +1643,10 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op)
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
- return C_O1_I1(r, L);
+ return C_O1_I1(r, r);
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- return C_O0_I2(LZ, L);
+ return C_O0_I2(rZ, r);
default:
g_assert_not_reached();
--
2.34.1
- Re: [PATCH v2 42/54] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path, (continued)
- [PATCH v2 44/54] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path, Richard Henderson, 2023/04/10
- [PATCH v2 45/54] tcg/loongarch64: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/04/10
- [PATCH v2 46/54] tcg/mips: Remove MO_BSWAP handling, Richard Henderson, 2023/04/10
- [PATCH v2 47/54] tcg/mips: Reorg tcg_out_tlb_load, Richard Henderson, 2023/04/10
- [PATCH v2 49/54] tcg/ppc: Reorg tcg_out_tlb_read, Richard Henderson, 2023/04/10
- [PATCH v2 51/54] tcg/ppc: Remove unused constraints A, B, C, D, Richard Henderson, 2023/04/10
- [PATCH v2 48/54] tcg/mips: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/04/10
- [PATCH v2 52/54] tcg/riscv: Simplify constraints on qemu_ld/st,
Richard Henderson <=
- [PATCH v2 50/54] tcg/ppc: Adjust constraints on qemu_ld/st, Richard Henderson, 2023/04/10
- [PATCH v2 54/54] tcg/s390x: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/04/10
- [PATCH v2 53/54] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st, Richard Henderson, 2023/04/10