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[PATCH v7 18/25] target/riscv: Hoist second stage mode change to callers
From: |
Richard Henderson |
Subject: |
[PATCH v7 18/25] target/riscv: Hoist second stage mode change to callers |
Date: |
Wed, 12 Apr 2023 13:43:26 +0200 |
Move the check from the top of get_physical_address to
the two callers, where passing mmu_idx makes no sense.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 38bd83f66d..5753e4e612 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -777,14 +777,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
use_background = true;
}
- if (first_stage == false) {
- /*
- * We are in stage 2 translation, this is similar to stage 1.
- * Stage 2 is always taken as U-mode
- */
- mode = PRV_U;
- }
-
if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -890,7 +882,7 @@ restart:
/* Do the second stage translation on the base PTE address. */
int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
base, NULL, MMU_DATA_LOAD,
- mmu_idx, false, true,
+ MMUIdx_U, false, true,
is_debug);
if (vbase_ret != TRANSLATE_SUCCESS) {
@@ -1271,7 +1263,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
im_address = pa;
ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
- access_type, mmu_idx, false, true,
+ access_type, MMUIdx_U, false, true,
false);
qemu_log_mask(CPU_LOG_MMU,
--
2.34.1
- [PATCH v7 06/25] target/riscv: Separate priv from mmu_idx, (continued)
- [PATCH v7 06/25] target/riscv: Separate priv from mmu_idx, Richard Henderson, 2023/04/12
- [PATCH v7 02/25] target/riscv: Add a general status enum for extensions, Richard Henderson, 2023/04/12
- [PATCH v7 05/25] target/riscv: Add a tb flags field for vstart, Richard Henderson, 2023/04/12
- [PATCH v7 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change, Richard Henderson, 2023/04/12
- [PATCH v7 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX, Richard Henderson, 2023/04/12
- [PATCH v7 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Richard Henderson, 2023/04/12
- [PATCH v7 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv, Richard Henderson, 2023/04/12
- [PATCH v7 19/25] target/riscv: Hoist pbmte and hade out of the level loop, Richard Henderson, 2023/04/12
- [PATCH v7 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Richard Henderson, 2023/04/12
- [PATCH v7 17/25] target/riscv: Check SUM in the correct register, Richard Henderson, 2023/04/12
- [PATCH v7 18/25] target/riscv: Hoist second stage mode change to callers,
Richard Henderson <=
- [PATCH v7 21/25] target/riscv: Suppress pte update with is_debug, Richard Henderson, 2023/04/12
- [PATCH v7 22/25] target/riscv: Don't modify SUM with is_debug, Richard Henderson, 2023/04/12
- [PATCH v7 24/25] target/riscv: Reorg access check in get_physical_address, Richard Henderson, 2023/04/12
- [PATCH v7 20/25] target/riscv: Move leaf pte processing out of level loop, Richard Henderson, 2023/04/12
- [PATCH v7 23/25] target/riscv: Merge checks for reserved pte flags, Richard Henderson, 2023/04/12
- [PATCH v7 25/25] target/riscv: Reorg sum check in get_physical_address, Richard Henderson, 2023/04/12
- Re: [PATCH v7 00/25] target/riscv: MSTATUS_SUM + cleanups, Alistair Francis, 2023/04/16