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[PATCH v7 19/25] target/riscv: Hoist pbmte and hade out of the level loo
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From: |
Richard Henderson |
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Subject: |
[PATCH v7 19/25] target/riscv: Hoist pbmte and hade out of the level loop |
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Date: |
Wed, 12 Apr 2023 13:43:27 +0200 |
These values are constant for every level of pte lookup.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 5753e4e612..7c9f89d4d3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -856,6 +856,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
return TRANSLATE_FAIL;
}
+ bool pbmte = env->menvcfg & MENVCFG_PBMTE;
+ bool hade = env->menvcfg & MENVCFG_HADE;
+
+ if (first_stage && two_stage && env->virt_enabled) {
+ pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
+ hade = hade && (env->henvcfg & HENVCFG_HADE);
+ }
+
int ptshift = (levels - 1) * ptidxbits;
int i;
@@ -916,14 +924,6 @@ restart:
return TRANSLATE_FAIL;
}
- bool pbmte = env->menvcfg & MENVCFG_PBMTE;
- bool hade = env->menvcfg & MENVCFG_HADE;
-
- if (first_stage && two_stage && env->virt_enabled) {
- pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
- hade = hade && (env->henvcfg & HENVCFG_HADE);
- }
-
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
} else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
--
2.34.1
- [PATCH v7 13/25] target/riscv: Introduce mmuidx_priv, (continued)
- [PATCH v7 13/25] target/riscv: Introduce mmuidx_priv, Richard Henderson, 2023/04/12
- [PATCH v7 14/25] target/riscv: Introduce mmuidx_2stage, Richard Henderson, 2023/04/12
- [PATCH v7 08/25] accel/tcg: Add cpu_ld*_code_mmu, Richard Henderson, 2023/04/12
- [PATCH v7 06/25] target/riscv: Separate priv from mmu_idx, Richard Henderson, 2023/04/12
- [PATCH v7 02/25] target/riscv: Add a general status enum for extensions, Richard Henderson, 2023/04/12
- [PATCH v7 05/25] target/riscv: Add a tb flags field for vstart, Richard Henderson, 2023/04/12
- [PATCH v7 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change, Richard Henderson, 2023/04/12
- [PATCH v7 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX, Richard Henderson, 2023/04/12
- [PATCH v7 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Richard Henderson, 2023/04/12
- [PATCH v7 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv, Richard Henderson, 2023/04/12
- [PATCH v7 19/25] target/riscv: Hoist pbmte and hade out of the level loop,
Richard Henderson <=
- [PATCH v7 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Richard Henderson, 2023/04/12
- [PATCH v7 17/25] target/riscv: Check SUM in the correct register, Richard Henderson, 2023/04/12
- [PATCH v7 18/25] target/riscv: Hoist second stage mode change to callers, Richard Henderson, 2023/04/12
- [PATCH v7 21/25] target/riscv: Suppress pte update with is_debug, Richard Henderson, 2023/04/12
- [PATCH v7 22/25] target/riscv: Don't modify SUM with is_debug, Richard Henderson, 2023/04/12
- [PATCH v7 24/25] target/riscv: Reorg access check in get_physical_address, Richard Henderson, 2023/04/12
- [PATCH v7 20/25] target/riscv: Move leaf pte processing out of level loop, Richard Henderson, 2023/04/12
- [PATCH v7 23/25] target/riscv: Merge checks for reserved pte flags, Richard Henderson, 2023/04/12
- [PATCH v7 25/25] target/riscv: Reorg sum check in get_physical_address, Richard Henderson, 2023/04/12
- Re: [PATCH v7 00/25] target/riscv: MSTATUS_SUM + cleanups, Alistair Francis, 2023/04/16