Re: [PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags

[Alistair Francis]

On Sat, Mar 25, 2023 at 10:35 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 850817edfd..82a7c5f9dd 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -976,14 +976,14 @@ restart:
>          /* Reserved without Svpbmt. */
>          return TRANSLATE_FAIL;
>      }
> -    if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
> -        /* Reserved leaf PTE flags: PTE_W */
> -        return TRANSLATE_FAIL;
> -    }
> -    if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
> -        /* Reserved leaf PTE flags: PTE_W + PTE_X */
> +
> +    /* Check for reserved combinations of RWX flags. */
> +    switch (pte & (PTE_R | PTE_W | PTE_X)) {
> +    case PTE_W:
> +    case PTE_W | PTE_X:
>          return TRANSLATE_FAIL;
>      }
> +
>      if ((pte & PTE_U) &&
>          ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
>          /*
> --
> 2.34.1
>
>