A CPU is declared static or not by changing the class attribute
'static'. For now the base class is defining every CPU as static via
riscv_cpu_class_init().
To change this setting for generic CPUs we'll need a different class
init for them. Then we'll ned a macro that allows us to set a different
.class_init implementation for the CPU. With all that we're now able to
set 'static' as false for the 'any', 'rv32', 'rv64' and 'x-rv128' CPUs.
For the riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
{"QMP": {"version": (...) }
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
{"return": {}}
{"execute": "query-cpu-definitions"}
{"return": [
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated":
false},
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true,
"deprecated": false},
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":
false},
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false,
"deprecated": false},
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true,
"deprecated": false},
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true,
"deprecated": false},
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true,
"deprecated": false}]
}
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 30a1e74ea6..4a9624404c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -340,6 +340,13 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
}
#endif
+static void riscv_any_cpu_class_init(ObjectClass *c, void *data)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
+
+ mcc->static_model = false;
+}
+
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -360,6 +367,13 @@ static void riscv_any_cpu_init(Object *obj)
}
#if defined(TARGET_RISCV64)
+static void rv64_base_cpu_class_init(ObjectClass *c, void *data)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
+
+ mcc->static_model = false;
+}
+
static void rv64_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -430,6 +444,13 @@ static void rv64_thead_c906_cpu_init(Object *obj)
#endif
}
+static void rv128_base_cpu_class_init(ObjectClass *c, void *data)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
+
+ mcc->static_model = false;
+}
+
static void rv128_base_cpu_init(Object *obj)
{
if (qemu_tcg_mttcg_enabled()) {
@@ -449,6 +470,13 @@ static void rv128_base_cpu_init(Object *obj)
#endif
}
#else
+static void rv32_base_cpu_class_init(ObjectClass *c, void *data)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
+
+ mcc->static_model = false;
+}
+
static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -1779,6 +1807,14 @@ void riscv_cpu_list(void)
.instance_init = initfn \
}
+#define DEFINE_CPU_WITH_CLASSFN(type_name, initfn, classfn) \
+ { \
+ .name = type_name, \
+ .parent = TYPE_RISCV_CPU, \
+ .instance_init = initfn, \
+ .class_init = classfn \
+ }
+
static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU,
@@ -1790,23 +1826,27 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_class_init,
},
- DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
+ DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init,
+ riscv_any_cpu_class_init),
#if defined(CONFIG_KVM)
DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
#endif
#if defined(TARGET_RISCV32)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
+ DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init,
+ rv32_base_cpu_class_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
+ DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init,
+ rv64_base_cpu_class_init),
+ DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init,
+ rv128_base_cpu_class_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};