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[PATCH 3/4] target/riscv: add 'static' attribute of query-cpu-definition
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH 3/4] target/riscv: add 'static' attribute of query-cpu-definitions |
Date: |
Mon, 10 Apr 2023 09:29:44 -0300 |
'static' is defined in the QMP doc as:
"whether a CPU definition is static and will not change depending on
QEMU version, machine type, machine options and accelerator options. A
static model is always migration-safe."
For RISC-V we'll consider all named CPUs as static since their
extensions can't be changed by user input. Generic CPUs will be
considered non-static.
We aren't ready to make the change for generic CPUs yet because we're
using the same class init for every CPU. We'll deal with it next.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu-qom.h | 3 +++
target/riscv/cpu.c | 6 ++++++
target/riscv/riscv-qmp-cmds.c | 2 ++
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index b9318e0783..687cb6f4d0 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -54,6 +54,7 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
+ * @static_model: See CpuDefinitionInfo::static
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
@@ -65,6 +66,8 @@ struct RISCVCPUClass {
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
+
+ bool static_model;
};
#endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cb68916fce..30a1e74ea6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1679,6 +1679,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
&mcc->parent_phases);
+ /*
+ * Consider all models to be static. Each CPU is free to
+ * set it to false if needed.
+ */
+ mcc->static_model = true;
+
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
cc->dump_state = riscv_cpu_dump_state;
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index 128677add9..639f2c052e 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -30,6 +30,7 @@
static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
+ RISCVCPUClass *cc = RISCV_CPU_CLASS(oc);
CpuDefinitionInfoList **cpu_list = user_data;
CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
const char *typename = object_class_get_name(oc);
@@ -37,6 +38,7 @@ static void riscv_cpu_add_definition(gpointer data, gpointer
user_data)
info->name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_RISCV_CPU));
info->q_typename = g_strdup(typename);
+ info->q_static = cc->static_model;
QAPI_LIST_PREPEND(*cpu_list, info);
}
--
2.39.2