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[PATCH 3/7] target/riscv: Change gen_goto_tb to work on displacements
From: |
Weiwei Li |
Subject: |
[PATCH 3/7] target/riscv: Change gen_goto_tb to work on displacements |
Date: |
Sun, 9 Apr 2023 18:53:02 +0800 |
Reduce reliance on absolute value to prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c | 8 +++++---
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index cc72864d32..f9a2464287 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -171,7 +171,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond
cond)
} else {
tcg_gen_brcond_tl(cond, src1, src2, l);
}
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+ gen_goto_tb(ctx, 1, ctx->cur_insn_len);
gen_set_label(l); /* branch taken */
@@ -182,7 +182,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond
cond)
gen_pc_plus_diff(target_pc, ctx, next_pc);
gen_exception_inst_addr_mis(ctx, target_pc);
} else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+ gen_goto_tb(ctx, 0, a->imm);
}
ctx->base.is_jmp = DISAS_NORETURN;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index eee13b1225..8c157d947e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -281,8 +281,10 @@ static void exit_tb(DisasContext *ctx)
tcg_gen_exit_tb(NULL, 0);
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
{
+ target_ulong dest = ctx->base.pc_next + diff;
+
/*
* Under itrigger, instruction executes one by one like singlestep,
* direct block chain benefits will be small.
@@ -557,7 +559,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong
imm)
}
gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
- gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety
*/
+ gen_goto_tb(ctx, 0, imm); /* must use this for safety */
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -1237,7 +1239,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
switch (ctx->base.is_jmp) {
case DISAS_TOO_MANY:
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
+ gen_goto_tb(ctx, 0, 0);
break;
case DISAS_NORETURN:
break;
--
2.25.1
- [PATCH 0/7] target/riscv: Add support for PC-relative translation, Weiwei Li, 2023/04/09
- [PATCH 7/7] target/riscv: Remove pc_succ_insn from DisasContext, Weiwei Li, 2023/04/09
- [PATCH 5/7] target/riscv: Use true diff for gen_pc_plus_diff, Weiwei Li, 2023/04/09
- [PATCH 1/7] target/riscv: Fix target address to update badaddr, Weiwei Li, 2023/04/09
- [PATCH 3/7] target/riscv: Change gen_goto_tb to work on displacements,
Weiwei Li <=
- [PATCH 2/7] target/riscv: Introduce cur_insn_len into DisasContext, Weiwei Li, 2023/04/09
- [PATCH 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc, Weiwei Li, 2023/04/09
- [PATCH 6/7] target/riscv: Enable PC-relative translation, Weiwei Li, 2023/04/09